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IPC Transport Mechanisms

RCReddy
Genius 3575 points

Hi All,

         I looked at data manual and this forum's posts, what i understand is as follows. [I am mainly looking at Core to Core data Communication]

MessageQ package sits on these transport mechanisms [SharedMemory,QMSS,HyperTransport,SRIO]

1. SharedMemory,QMSS based IPC can be used across cores only. between chips c6670 both are not possible

2. IPC sitting over SRIO is possible between two chips c6670 chips.

3. I understand from one of the Ti's post is that even EDMA can do both jobs [point 1 and point 2] and it is much faster. Is it possible to MessageQ over EDMA3.

4. Till now my understanding is that, between chips its SRIO and between cores, it should be qmss [pend queue] or shared memory. My question is where does the EDMA3 fit in here.

please explain what is difference betwen EDMA3 transport mechanism and IPC[qmss ] transport mechanism and which is appropriate [in terms of less cyles and maximum data transfer ability]

Thanks

R c Reddy

  • 0
    TI__Intellectual 2415 points

    Hi Reddy,

    Please, find my answers inserted below:

    3. I understand from one of the Ti's post is that even EDMA can do both jobs [point 1 and point 2] and it is much faster. Is it possible to MessageQ over EDMA3.

    [Karthik]: EDMA3 cannot be used for chip to chip communication. As far as I know, TI does not support core to core IPC over EDMA3. Other experts in this forum can correct me here if I am wrong.

    4. Till now my understanding is that, between chips its SRIO and between cores, it should be qmss [pend queue] or shared memory. My question is where does the EDMA3 fit in here.

    [Karthik]: Your understanding until now is correct. EDMA3 is not supported as a IPC transport mechanism.

    I hope this helps.

  • 0 in reply to Karthik Ramana Sankar
    Genius 3575 points

    Hi Karthik,

                       wait, let me put the actual link 

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/152826.aspx

    http://www.ti.com/lit/an/sprabk5/sprabk5.pdf

    what i meant by IPC is Simple data transfer, by two of the above web links, I am certain that EDMA can be used for CHIP to CHIP and CORE to CORE Transfer [please get back with expert answers, so that i can go in right direction].

    so concern is, is there anyway i can link the MessageQ's [MessageQ is a simple mechanism which sits over Hyperlink,SRIO,QMSS,Shared Memory] over EDMA data transfer. Since Hyperlink is also a Transport mechanism [i assume Hyperlink is the actual physical layer which does the DMA'ing which is initiated by EDMA controller], so MessageQ should be possible over Hyperlink/EDMA.If it is so, please point me to the literature.

    Thanks

    RC Reddy

  • 0 in reply to RCReddy
    TI__Intellectual 2415 points

    Hi Reddy,

    I would like to state my point more clearly here: Standalone EDMA3 cannot be used for chip to chip communication. Where as, EDMA coupled with Hyperlink can be used for chip to chip communications. As far as my knowledge, we do not have SYS/BIOS IPC layer implemented over EDMA3. The EDMA3 LLD provides the high level abstraction, which can be used to program EDMA3 transfers. The following IPC examples are available in C6678 PDK (<CCS_INSTALL>\pdk_C6678_1_0_0_XX\packages\ti\transport\ipc\examples):

      1) QMSS Infrastructure DMA

      2) SRIO (core to core and chip to chip)

    The above are just examples, these examples can be modified accordingly to perform chip to chip IPC over Hyperlink. I am not saying that EDMA3 cannot be used to perform core to core IPC, it can definitely be used for core to core IPC, but we do not have examples or code showing this type of usage. My understanding is that, EDMA3 is more suited for peripheral to memory data transfers, triggered by an event from the peripheral.

    I hope this helps.