hello,experts
I'm using codec engine example of videnc_copy to do my own video encoding work.
Now I have completed the codec,server and app source code. So I wonder where to config my DSP memory layout like in file " link.cmd " of CCS project .I have read the "codec engine aplication developer/server integrator/algorithm creator user guide" but find no answer.
for example in a c6a816x.cmd file,there are some memory layout like below:
-heap 0x400000
-stack 0x2000
MEMORY
{
DSPL2 o = 0x00800000 l = 0x00040000 /* 256kB DSP L2 RAM */
DSPL1P o = 0x00E00000 l = 0x00008000 /* 32kB DSP L1 Program Cache/RAM */
DSPL1D o = 0x00F00000 l = 0x00008000 /* 32kB DSP L1 Data Cache/RAM */
L3OCMC0 o = 0x40300000 l = 0x00040000 /* 256kB L3 OCMC SRAM */
L3OCMC1 o = 0x40400000 l = 0x00040000 /* 256kB L3 OCMC SRAM */
SHDSPL2 o = 0x40800000 l = 0x00040000 /* 256kB Shared DSP L2 RAM */
SHDSPL1P o = 0x40E00000 l = 0x00008000 /* 32kB Shared DSP L1 Program Cache/RAM */
SHDSPL1D o = 0x40F00000 l = 0x00008000 /* 32kB Shared DSP L1 Data Cache/RAM */
DDR0 o = 0x80000000 l = 0x40000000 /* 1GB external DDR Bank 0 */
DDR1 o = 0xC0000000 l = 0x40000000 /* 1GB external DDR Bank 1 */
}
SECTIONS
{
.text > DDR0
.stack > DDR0
.bss > DDR0
.cio > DDR0
.const > DDR0
.data > DDR0
.switch > DDR0
.sysmem > DDR0
.far > DDR0
.args > DDR0
.ppinfo > DDR0
.ppdata > DDR0
/* TI-ABI or COFF sections */
.pinit > DDR0
.cinit > DDR0
/* EABI sections */
.binit > DDR0
.init_array > DDR0
.neardata > DDR0
.fardata > DDR0
.rodata > DDR0
.c6xabi.exidx > DDR0
.c6xabi.extab > DDR0
}
I just want to know how to do this work in codec engine examples.Thank you very much!