For those of us using cache, I think the IRQHandler and FIQHandler should replace the DMB instruction with the DSB instruction. DMB is a subset of DSB.
Note
mcr p15 0, r0, c7, c10, 4 ;;same as DMB (Data Memory Barrier)
mcr p15, 0, r0, c7, c10, 4 ;; same as DSB (Data Synchronisation Barrier)
Anyway, I am not 100% sure about this but ARM has at least one 28 page document I found about DSB, DMB, ISB.