Does mcfw support 5M pixel ipcam decode and display?

Hi,

I see the spec sprugx8_dm816x_vpss.pdf, the register of  source width only have 11Bits, it means the max width only can be 2047. Is it possible to do two times scale for big than 2048 resolution scale in the DVR RDK?

Jacson

Dear Jacson,

All the modules of HDVPSS supports maximum line width of 1920. There is not limit on the number of lines though.  IP recommended clock frequency for both capture and display is 165MHz. Also HDVPSS drivers will support non-standard resolution where user can input the various timing parameters like pclk, hsync, vsync, hbp, hfp, vbp,vfp and width and height of the required non-standard resolution. In summary HDVPSS can support any resolution which requries pixex clock <= 165MHz.

B.R.

OC

Dear OC,

Thanks for your reply.

I want to decode ipcam bitstream resolution more than 2k x  2k and display, I know the codec has ability to do big resolution decode, but software mosaic seems become a limitation to do mosaic and display. Is it possible to let software mosaic support input resolution more than 2k x 2k? Does the scalar ability limit at the pixel clock your mention? I can't understand your mean, could you please explain more clear for me?

Very thanks!

Jacson

Dear OC,

This function will be available on next rdk release? and when will release the new rdk? May I know the schedule?

Thanks,

Jacson