• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 200 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BDEC register behaviour

steve duncan
Prodigy 85 points


Hi,

C66 CPU and Instruction Set Reference (SPRUGH7) says about BDEC that the loop count register is updated after the branch has been taken (Example 1, page 4-67).

The C66x simulator displays the loop count register as being updated in the cycle immediately after the loop instruction, i.e. 4 cycles before the branch is taken.

Which is correct?  If the latter, please update Examples 1 and 2 in the documentation, as they are misleading.

  • 0
    TI__Mastermind 30825 points

    Steven,

    The C66 CPU and Instruction Set Reference Guide (SPRUGH7) BDEC Example does not say when the loop count is updated.  It only shows what was before the BDEC instruction and after it's branch has been taken.  That said, it's update immediately upon execution, this is shown in the Pipeline Figure on the same page.  The loop count is in the dst register, note that it is updated in the pipeline at the original E1 stage.  That said, I did notice a mistake, the original E1 indicates the PC is updated at that stage, when in fact it's PFC (Program Fetch Count) which begins the piping up of the program where it's branching to.  I'll note that this needs to be corrected.

    Best Regards,

    Chad