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DDR2 layout on DM365

Omin Chou
Genius 3555 points

Dear all,

I had checked DM365EVM layout file on DDR2 trace as below.

1. DDR_GATE0 to DDR_GATE1: 2511.97(383.08+2128.89)

2. CLKP: 1590.79(738.12+852.67)

3. DQ0~15: 1374.148(average)

The DM365EVM schematic had mentioned that the DDR_GATE net is equal to the DDR_CLKP ( or DDR_CLKN ) plus the length of DDR_DQXX average trace length. But  the length is 2511.97 not 2964 in the EVM layout. Can anyone help me to explain this portion? Thanks in advance.

B.R.

OC

 

 

 

 

  • 0
    Intellectual 565 points

    Hi OC,

    It is hard to determine exactly what the board designer had in mind, but I can offer a couple suggestions. It may have simply been an oversight. Or the designer may have (incorrectly) used a target length of 2 * Average(DQ[0:15]). Or the designer may have added length for vias if any exist (I don't have the board file in front of me so I cannot say for sure on this one.)

    One thing to note on the routing guidelines given in the datasheet - they tend to be on the conservative side so that if you follow them, your board is very likely to work. However, it is possible to relax some of the routing guidelines and still have a rock solid design.

    Good luck!

    JPM