Hi,
I have posted a EMIFA issue that we are facing currently in Processor forums.
The basic HW design was we have connected a CPLD and 4-Channel External UART Controller on EMIFA using different chip selects.
From CPLD data will be read by EDMA. EDMA will get a GPIO event for every 2-Bytes. (CPLD will have 64 * 1000, 16-bit data per second. So EDMA gets a total of 64000 events per second.
While reading from CPLD, it is observed that while we read from UART some bytes are dropped. If we disable ADC reading the UART driver is able to read data from conencted UART devices without any issues.
Following is the URL that I have posted the same in Processor Forum.
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/185438.aspx
Please let me know if you have any suggestions and Thank You for your time
Regards,
GSR