I'm using a 6482. I have an FPGA connected via EMIFA (synchronous). I have external RAM connected via DDR2 Memory Controller.
I have a high priority thread that processes an interrupt from the FPGA and starts a DMA transfer from the FPGA to internal memory.
I have a low priority thread that chugs on the data and uses external RAM.
It appears that the DMAs from EMIF take longer to complete when the low priority thread is running.
I assumed I needed to adjust the priorities on the SCR.
But in sprs246k section 4.4, it says the default priority has the EDMA3 as the highest priority.
Other ideas? Something I am missing?
thanks,
Brad
