I have already posted a message to the Arago email list with more detail, but I think this problem is more hardware related than software.
I am using Arago Linux v2.6.37_DAVINCIPSP_03.21.00.04 on an OMAP-L138. By adding a bunch of print statements and debug code, and observing the baud rate of the serial terminal (UART2), it appears that ASYNC3 cannot source from PLL1 SYSCLK/2. Rather, the register CFGCHIP3 updates properly when written to make a change over to PLL1, but the baud rate of the serial terminal reflects the rate of PLL0.
Some details of my setup:
20 MHz oscillator
UBL setup as follows:
status |= DEVICE_PLL0Init(0, 19, 0, 0, 0, 31, 7);
status |= DEVICE_PLL1Init(14, 0, 0, 1, 5);
PLL0 outputs at:
SYSCLK1 - 400 MHz
SYSCLK2 - 200 MHz
SYSCLK3 - 12.5 MHz
SYSCLK7 - 50MHz
and PLL1:
SYSCLK1 - 300 MHz
SYSCLK2 - 150 MHz
SYSCLK3 - 50 MHz
In linux I changed the "OPP" to reflect these settings, and made other necessary changes to make sure the kernel keeps these PLL settings..
When switching ASYNC3 to PLL1, the baud rate of UART2 reflects an ASYNC3 input of 200MHz. The measured baud rate is 154000, the UART divider is 81. This is all verified with print statements.
One peculiar thing I noticed from TI's clocking spreadsheet is that 200MHz is not a permissible value for ASYNC3. I don't know if that would somehow prevent the hardware from switching from the 200MHz PLL0 clock to the 150MHz PLL1 clock source.
Thanks
- Judson
