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SPI max data rate?

Calum Mackinnon
Genius 4155 points


Hi,

I see in the first few pages of the data sheet that the McSPI serial interface has a max clock rate of 48MHz - I couldn't timing diagrams or max clock rates for the modes of operation - where can I find that info - all the links to the TRM seem to be broken.

Calum

  • 0
    TI__Guru 63385 points

    We are currently in the process of adding the McSPI timing information to the data sheet.  We plan to have this completed by the end of the month.

    Thanks for letting us know about the TRM links.  A new version was being released today.  This may be a temporary issue while the new one is coming online.  I have reported the issue so hopefully it will be resolved soon. 

    Regards,
    Paul

  • 0
    TI__Prodigy 270 points

    Hi Calum,

    It looks like the TRM link is working again. Give it a try.

  • 0 in reply to peaves
    Expert 2280 points

    Hi

    I have a question related to SPI max frequency so I'm continuing on this thread. Accordingly to data-sheet and TRM, max frequency for AM335x SPI is 48 MHz.

    For this reason I cannot understand SPL/U-Boot configuration code for SPI Flash: OMAP3_MCSPI_MAX_FREQ is defined as 80000000 in omap3_spi.h under CONFIG_AM335X, and CONFIG_SF_DEFAULT_SPEED is set to 75000000 in am335x_evm.h. With these values the omap3_spi.c driver calculates the channel frequency divider to 2, making SPI to work at 24 MHz. Is it as expected? Are these defines typos to be fixed as 48000000 and 24000000?

    Thanks for any clarification. Regards

    Max

  • 0 in reply to Qmax
    Prodigy 40 points

    Hi, Max,

    This is a issue just confused me.

    I don't know whether you can let it work on 48MHz, but for me if change the divider to 1 let it work in 48Mhz, then the system can not read the SPI nor flash ID correctly, and system will crashed. Neither for U-Boot nor linux kernel.

    Is there an TI emploee help me on this issue?

    Regards,

  • 0 in reply to Sword Liu
    Expert 2280 points

    Hi

    Unfortunately nobody from TI confirm my note, but comparison between U-Boot and Linux source code is quite clear: the first states OMAP3_MCSPI_MAX_FREQ 80000000, the second OMAP2_MCSPI_MAX_FREQ 48000000. And the two SPI drivers use these as upper value to calculate the value of CLKD field bits in MCSPI_CH(i)CONF register. CLKD field bits value determines the divider to be used.

    Now, what I've done is just to modify required frequency (CONFIG_SF_DEFAULT_SPEED in U-Boot, and .max_speed_hz in Linux spi platform data) to make CLKD field bits to be set to 0, which accordingly to TRM leads to a divider equal to 1, thus 48 MHz as final frequency. While original values (75000000 and 24000000) makes CLKD filed bits to be set to 1, i.e. divider equal to 2 and 24 Mhz as configured frequency.

    I did not found any issue with this change: for sure no one with our custom boards, but I am pretty sure to have tested also with EVM. Which hardware platform are you using? EVM or custom one?

    Regards,
    Max

  • 0 in reply to Qmax
    Prodigy 40 points

    Hi,

    Yes, now I can let the EVM work on 48MHz in uboot, but must change the POL, I think maybe it relative with hardware issue. And I test the access speed, it has no help on 48Mhz than 24Mhz. Then I try to use FIFO buffer, this has help in uboot.

    However, if change to 48Mhz in kernel, it won't work. And I try to use FIFO on 24Mhz with DMA transfer, but any ways it can not work now, is there anybody also concerned AM335x SPI's speed, any advice?

    Regards,