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Cache disabling

RCReddy
Genius 3575 points
Other Parts Discussed in Thread: SYSBIOS

Hi All,

           Is Cache disabling static ?[static i mean here is, it is onetime initialize and it will be there forever] or is it dynamic. My doubt is couple of times in this forum "Cache disabling is suggested [for example http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/150938.aspx]", but that may kill the real time computation within specified time limits, so in this situation what is the best way to handle. [so is this cache disabling and enabling dynamic ?].

i am mainly talking about these two lines [pasted below]

CACHE_setL1DSize(CACHE_L1_0KCACHE);

CACHE_setL2Size(CACHE_0KCACHE);

Thanks

RC Reddy

  • 0
    TI__Mastermind 32475 points

    RC,

    What is it that you actually want to do?

    Cache disabling is dynamic because you can disable() and enable() anytime in your *.c code.  I don't recommend disabling the cache except if you need to do it for a very specific reason.  A better way would be to disable portions of your memory map from being cacheable.  This is done through the MAR bits for the C6000 family of DSPs.

    Judah

  • 0 in reply to judahvang
    Genius 3575 points

    Hi Judah,

                     Thanks for answer. Here is the reason why i want/need to do it.

    1,Core 2 creates a Heap and MessageQ and is waiting for Message on MessageQ

    2. Core 0,Core 1 and Core 3 opens the Heap and Messageq and puts the data on MessageQ. what i see is messages from Core0 and Core1 are received and MessageQ_get() is waiting [WAIT_FOREVER] for Core 3. 

    3. Core3 does MessageQ_Put() successfully [i see the returned Integer status as zero = successful] and 

    4. when i disable caching [the lines are pasted in earlier post], I see Core 2 gets the Message in MessageQ from Core3. A cache disabling is helping me in getting the Message [so i wonder if there is a genuine bug in the MessageQ Module] [i tested it both on simulator and c6670 board also, the behaviour is same] [i posted this as a question at this link

    http://e2e.ti.com/support/embedded/bios/f/355/p/185552/670737.aspx#670737]

    Thanks

    RC Reddy 

     

  • 0 in reply to RCReddy
    TI__Mastermind 32475 points

    RC,

    You shouldn't have to do that.  Can you please specificy what processor you are running your code on?  Is it The 6670?

    Have you tried the IPC example that comes with the CCS installation?  It has a very simple messageQ example.

    Judah

  • 0 in reply to judahvang
    Prodigy 65 points

    Hi Judah,
    I tried that example sometime back [It works, no doubt about it]. I built my own project and it is being made to run on C6670 evm board. So, tell me a way to make/force the cache contents to be put onto actual memory location [i recall i saw some API, but coulnd't track it] [is that a correct solution ?].
    Thanks

  • 0 in reply to Deepu N
    TI__Mastermind 32475 points

    Deepu,

    If you are using SYS/BIOS we have a set of Cache APIs that allow you to do this.

    The module can be found in your installation at:  <INSTALL>/packages/ti/sysbios/family/c64p/Cache.c

    The APIs are:
    Cache_wb() - Cache writeback
    Cache_inv() - Cache invalidate
    Cache_wbInv() - Cache writeback invalidate

    Judah

  • 0 in reply to judahvang
    Genius 3575 points

    Thanks,

                   For reply,

    RC Reddy