I'm looking for specs on the McASP timing within the AM3352 processor. I will be using an external 24.576MHz VCXO and PLL to bring a Master Clock into the AHCLKx pin and then use the internal divider (usually divide by 2) to generate a bit clock, ACLKx which will be buffered and sent to several parts in the system. That clock will also be used internal to the McASP to generate the frame sync for both the transmit and receive data. I'm looking at a large stack up of delays between the master clock in and getting data back from ADCs through an external DSP, so I need to know how much I need to allow for within the McASP internal gates. Specifically I need the numbers for:
AHCLKx IN to ACLKx OUT delay timing
AHCLKx IN to FSx out delay timing
AHCLKx IN to internal Frame Sync for receive data delay timing
AHCLKx IN to data TX OUT delay timing
if these specs are all generally expected to be less than a couple nanoseconds, they are probably negligible, but any more than that and I need to add them to the full audio clocking timing analysis for the system. Thanks for the help!
