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.ivec opcodes ?

Jon Halland
Prodigy 180 points

Hi

When using the directives:

_RST:    .ivec    _Reset, USE_RETA  ; Reset / Software Interrupt #0

NMI:     .ivec    nmi_isr        ; Nonmaskable Interrupt

The following opcodes are generated

CA<P24 address>  : a branch or call with 24-bit address encoded

5E80_5F80            : NOP_16 || NOP_16 

EA<P24 address>  : a branch or call with 24-bit address encoded

5E80_5F80            : NOP_16 || NOP_16

These interrupt vector branch or call instructions do not seem to be ducumented in the C55x v3x instruction guides.

Where can I find info on them ?

Cheers

 

  • 0
    TI__Guru* 84285 points

    Assembler directives are documented in the Assembly Language Tools User's Guide.  You can find the C55x Assembly Language Tools User's Guide at http://processors.wiki.ti.com/index.php/TI_Compiler_Information#Compiler_Manuals.  See SPRU280I page 113

  • 0 in reply to Archaeologist
    Prodigy 180 points

    Hi Archaeologist,

    First, thanks for the reply. I am aware of the .ivec description in spru280i but it does not cover a description of the instructions inserted by the .ivec directive.

    And when not able to find a description or look-up the op codes in swpu067e the question arise:

    What do these instructions actually do ?

    I ask the question because I never use more memory than necessary (it will always be needed later). Having to branch to another location just to implement a catch

    of a spurious interrupt that could be implemented with a simple goto placed in the interrupt vector table, seem wastefull.

    The instruction in the reset location of the interrupt vector set the stack configuration (swpu073e p44), is there other functionality build in here ?

    The instructions placed at other interrupt locations have a diffrent opcode from an unconditional branch (6A<P24>), is there other functionality build in here ?

    Cheers

     

  • 0 in reply to Jon Halland
    TI__Guru* 84285 points

    SWPU067 is the C55x v3.x CPU Mnemonic Instruction Set Reference Guide. You won't find a description of .ivec there; although the bits in an interrupt vector resemble a branch instruction, the entries are not instructions. You need to look in SWPU073, the C55x v3.x CPU Reference Guide. SWPU073E section 4.2 "Stack Configurations" discusses the stack encoding in .ivec. SWPU073E section 5.2 "Interrupt Vectors and Priorities" paragraph 2 discusses the encoding of the vector table.

  • 0 in reply to Archaeologist
    Prodigy 180 points

    Hi Archaeologist

    From my previous post you can see that I'am avare of the stack configuration described in swpu073e.

    The .ivec directive DO place instructions in the interrupt vectortable. If not, how would the CPU be able to branch to an isr ?

    Thats why the <P24> address is encoded there. Try placing a normal branch <P24> in the interrupt vector table and execute it.

    Questions still remain:

    What do these undocumented instructions actually do ?

    Cheers

  • 0 in reply to Jon Halland
    TI__Guru* 84285 points

    They look like instructions, but they are not really. 

    The first 8 bits of the RESET slot of the interrupt vector are interpreted differently than normal code.  Those bits cannot be used elsewhere.

    On early C5500 prototypes, which had only one stack mode, they really were instructions, but when the new stack modes were added, the hardware was changed to treat those bits as data.  For backward compatibility, the 8-bit bit-pattern for the opcode for 24-bit absolute branch was defined to be one particular stack mode, and a couple of other 8-bit bit-patterns were chosen to represent the other two stack modes.

    If you must think of them as undocumented instructions, they mean "set the stack mode to mode X and branch to this 24-bit address."  Note that this meaning is only valid in the RESET slot of the interrupt vector.

  • 0 in reply to Archaeologist
    Prodigy 180 points

    Hi Archaeologist

    Thank you for your answers!