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What should be added to enhance the performance of the program based on the example video_loopback?

Other Parts Discussed in Thread: TVP5150

    Hi. Now I'm using DM6437 to do some video processing. My program is based on the given example video_loopback. In this original example, only the TVP5150, VPFE and VPBE are configured. However, since the data blocks are stored in DDR2 memory, I add some EDMA configurations to implememt block move between DDR2 memory. However,  the performance of my program was quite poor, in another words, it was very slow... I tried to add some register configuration to control the L2 cache, but there was no marked enhancement. My questions are:

1. If I configure the cache correctly, should I get obvious improvement on execution  speed?

2. Is there any problem in my L2 cache configuration? My codes concerned L2 cache is quite simple.

    CACHE_L2CFG = 0x00000007;      // define the size of L2 cache(maximum)

    it made no obvious change on performance.

    If I add this

    *(Uint32 *)0x01848200 = 1;     //// enable Memory Atrribute registers MAR128 & MAR129 corresponding memory address is 80000000h~81FFFFFFh
    *(Uint32 *)0x01848204 = 1;

    I do this because most of my data are stored in that area. However, when I add this to the program, the system halted when I began running.

3. Should I add some other configuraion to achieve better performance?

  • Here is a generic function to setup your L1P, L1D, & L2 cache for maximum size and set all of DDR2 as cacheable.  All the register defines are contained in the spectrum digital include files that come with the dev kit.  If you are going to go to the trouble of hard coding register addresses, make sure you address them as volatile.  It's much easier to just track down the include file.  Be sure to set the SIZE_DDR2 constant that is appropriate for your board.
    
    
    void cacheInit()
    {
    	volatile Uint32 *marPtr;
    	Uint32 i;
    
    	#define SIZE_DDR2 		0x10000000
    	#define MAR_STEP_SIZE	0x01000000
    
        CACHE_L1PINV = 1;	// L1P invalidated
        CACHE_L1PCFG = 7;	// L1P on, MAX size
        CACHE_L1DINV = 1;	// L1D invalidated
        CACHE_L1DCFG = 0;	// L1D off
        CACHE_L2INV  = 1;	// L2 invalidated
    	CACHE_L2CFG = 3; 	// 128k L2 cache enabled
    	i = CACHE_L2CFG;	// read register to setup cache mode change
    
    	marPtr = (volatile Uint32 *)0x01848200;	// base of ddr2 @ 0x80000000
    
    	for (i = 0; i < SIZE_DDR2; i+= MAR_STEP_SIZE) {
    		*marPtr++ = 1;
    	}
    
    	CACHE_L1DCFG = 0x00000004; // grab 32k of cache
    	i = CACHE_L1DCFG;	// read register to setup cache mode change 
    }