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How to configure the priority between the Ethernet ports

How is the priority between two CPGMAC_SL Ethernet ports configured?

Best regards,

Daisuke
 
  • Daisuke,

    Are you wanting to configure the Ethernet Class of Service (CoS) priority levels or the physical port priority levels?

  • Hi -DK-,

    Thank you for your reply.

    I am wanting to configure the internal port priority levels.

    I saw the CPSW_3G Block Diagram(Figure 14-6) in the TRM(SPRUH73E) and found out that each CPGMAC_SL has a single GMII interface.
    Therefore, I thought that the internal port priority levels depended on CPGMAC_SL.

    Best regards,

    Daisuke

     

  • I would like to clarify something related to the AM335x  Gigabit Media Independent Interface (GMII) signals.

    Each CPGMAC_SL natively contains a GMII port which can be internally multiplexed a GMII to RMII gasket, GMII to RGMII gasket, or to a subset of AM335x MII pins.  Only the GMII signals required to implement MII were multiplexed directly to pins.  This allows each  CPGMAC_SL to be connected to a 10/100 Mbps RMII PHY via the GMII to RMII gasket, a 10/100/1000 Mbps RGMII PHY via the GMII to RGMII gasket, or a 10/100 Mbps MII PHY via the subset of AM335x MII pins.

    We retained the GMII signal names for the pins since this matched the internal signal names which are also references in the CPSW documentation.  However, the upper four bits on each data path and the source-synchronous transmit clock signals were not connected to pins to reduce the number of pins.  This limits the GMII signals to MII operation.

    This may cause someone to think they can connect a GMII PHY.  Therefore, I wanted to clarify this before someone spends time trying to connect a GMII PHY.

    Regards,
    Paul

  • Daisuke,

    There is no way to set internal port priority levels, however, depending on your application you may find that traffic shaping via the Rate Limit Mode discussed in section 14.3.2.10.3 of the TRM (SPRUH73E) could serve your purpose by limiting one port to a lower ingress/egress rate than the other. Again, this would depend on the nature of your application and traffic.

  • Hi -DK-,

    Thank you for your reply.

    Are there the configurations (except the Rate Limit Mode) which affect the internal traffic?

    Best regards,

    Daisuke

     

  • Daisuke,

    The switch also supports QoS (Quality of Service) via the Priority Code Point bits of the 802.1Q header in the Ethernet frame which could be used to shape traffic internally; there are no other methods to control port priority from a hardware standpoint.

  • Hi -DK-,

    Thank you for your help.

    Best regards,

    Daisuke

  • Hi Daisuke Maeda,


    For Qav operation, the functional features of CPSW_3G that will have to be configured are mentioned below (referenceDRA7xx Infotainment Applications Processor Silicon Revision 1.0 data sheet) :

    1.DESCRIPTORS and CHANNEL CONFIGURATIONS:
    – CPPI TX and RX descriptors
    – VLAN and Priority tags

    TX DMA CHANNEL Packet Priority Switch Queue Priority
    7 7 3
    6 5 2
    5 3 1
    4 1 0


    2.ALE Configuration:
    – ALE in VLAN-ware mode, Non-ALE in bypass mode.


    Register Value Description

    CPSW_PTYPE 0x0006 0000 For Port1 -- 2 highest priority channels.

    P1_TX_IN_CTL[ 23:20] 0b1100 2 highest priority channels are
    TX_RATE_EN rate limited

    P1_TX_IN_CTL[17:16] 0b10 Rate limit mode
    TX_IN_SEL

    P1_SEND_PERCENT 0x14 3E00 20% PRI7, 62% PRI5

    CPDMA_DMACONTROL 0xC001 Chan7, Chan6 are Rate
    Limited.

    CPDMA_TX_PRI7_RATE 0x1 0013 200 Mbps

    CPDMA_TX_PRI6_RATE 0x1 0005 ~600 Mbps


    Could you please suggest that how to configure the above?