How is the priority between two CPGMAC_SL Ethernet ports configured? Best regards, Daisuke
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
How is the priority between two CPGMAC_SL Ethernet ports configured? Best regards, Daisuke
Hi -DK-,
Thank you for your reply.
I am wanting to configure the internal port priority levels.
I saw the CPSW_3G Block Diagram(Figure 14-6) in the TRM(SPRUH73E) and found out that each CPGMAC_SL has a single GMII interface.
Therefore, I thought that the internal port priority levels depended on CPGMAC_SL.
Best regards,
Daisuke
I would like to clarify something related to the AM335x Gigabit Media Independent Interface (GMII) signals.
Each CPGMAC_SL natively contains a GMII port which can be internally multiplexed a GMII to RMII gasket, GMII to RGMII gasket, or to a subset of AM335x MII pins. Only the GMII signals required to implement MII were multiplexed directly to pins. This allows each CPGMAC_SL to be connected to a 10/100 Mbps RMII PHY via the GMII to RMII gasket, a 10/100/1000 Mbps RGMII PHY via the GMII to RGMII gasket, or a 10/100 Mbps MII PHY via the subset of AM335x MII pins.
We retained the GMII signal names for the pins since this matched the internal signal names which are also references in the CPSW documentation. However, the upper four bits on each data path and the source-synchronous transmit clock signals were not connected to pins to reduce the number of pins. This limits the GMII signals to MII operation.
This may cause someone to think they can connect a GMII PHY. Therefore, I wanted to clarify this before someone spends time trying to connect a GMII PHY.
Regards,
Paul
Daisuke,
There is no way to set internal port priority levels, however, depending on your application you may find that traffic shaping via the Rate Limit Mode discussed in section 14.3.2.10.3 of the TRM (SPRUH73E) could serve your purpose by limiting one port to a lower ingress/egress rate than the other. Again, this would depend on the nature of your application and traffic.
Daisuke,
The switch also supports QoS (Quality of Service) via the Priority Code Point bits of the 802.1Q header in the Ethernet frame which could be used to shape traffic internally; there are no other methods to control port priority from a hardware standpoint.