I've been looking at the switch test project supplied with the eZDSP5535 to understand how the CSL API works and how to use it for the SAR ADC. I traced through the code and I found something that I couldn't quite understand. The GEL files for this project setup the PLL for 100MHz, setting the system clock to 100MHz, and then the code sets the SARCLKCTRL = 0x0B. This will give a divisor of 0x0C according to the datasheet. This I believe should set the FSAR_Clk = 100MHz/12 = 8,333,333 Hz. This is ~6MHz higher then what the datasheet says is the maximum for the SAR_Clk.
I'm I not catching something here or is the project incorrect for the SAR ADC? Thanks very much!
David Steele