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SRIO DirectIO v/s Message Passing

RCReddy
Genius 3575 points

Hi All,

I did study literature on direct I/O and Message Parsing based SRIO [Keystone architecture Serial Rapid IO User Guide].

1. Can i get any guidelines [provided by Ti] for choosing one over another.

2. Also i am looking at [i am mainly looking in terms of speed,number of cycles] benchmark results something like this [http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide#Benchmark_Results].

Thanks

RC Reddy

  • TI__Mastermind 23525 points

    Hi,

    1)  This really depends on what you are trying to do, i.e. what are you interfacing to, what type of memory management you have, what packet types you need.  There are a lot of things to consider here.  Bottom line, for DIO, the sender has to know the memory map of the receiving device, where in messaging it doesn't.  Messaging however is a little more involved regarding setup with QMSS.  Maybe if you have specific questions and more detail on what you want to do, it would be easier to figure out and recommend.

    2)  Check out :http://www.ti.com/lit/an/sprabk5/sprabk5.pdf section 14.1.  This will give you benchmarks for using the SRIO transfer modes without the overhead of IPC which sits on top of the messaging only layer.

    Regards,

    Travis

  • in reply to tscheck
    Genius 3575 points

    Hi tscheck,

                        your point 2) help me. Thanks for that. 

    Regarding point 1, i wanted to do SRIO based data transfer bw two c6670 chips [MessageQ MessagePassing over SRIO] and mono-qpend-QMSS between two cores [core to core communication] in same chip [c6670]

    Requirements: - 

    Max data throughput for SRIO stands at around 700Mbps [chip to chip].

    please suggest, will MessageQ[Message Passing SRIO and mono-qpend qmss] be suffice for both core to core and chip to chip communication. [the other thing to think is the MSMCSRAM will be used for MessageQ's]

    Thanks

    RC Reddy

  • in reply to RCReddy
    TI__Mastermind 23525 points

    RC,

    The SRIO IPC will work for chip-to-chip and the QMSS will work for the core-to-core as you suggest.  I can't comment on the throughput performance aspect of SRIO IPC directly, but it will be less that going strictly with the LLD.  If your goal is to keep the same API for both types of communication, then try to use the IPC first. 

    Regards,

    Travis