Decoding and Encoding capabilities issue/question in EVM8168 , SDK 5.04

Sobolevsky Vladik

Hi,

We are using following OMX application pipeline : File(1080p30)->VDEC->DEI(1080p30)->Display

|_VENC

We have 2 such pipelines running simultanesly so in total we have : 2 1080p30 Decode and 2 Encode.

The problem is that in Encoding we can only use 480p30 resolution , if we try 720p30 the VENC component will not transfer to Idle state.

The exactly same code works fine with 480p30 resolution.

So the question is where is the limitation ? in OMX implementation ? in Ducati code ?

Form the hardware spec we understand there is 3 HDVICP units which should be enough to handle these loads.

Please Advise,

Vladik

over 13 years ago

0 Sobolevsky Vladik over 13 years ago

Prodigy 240 points

Another addition is that , when running sys_top I see that only Sr0 is used in HDVICP .

So I think we just utilize single core for this . How can we extend the usage to other cores via OMX ?

0 Anirban Sengupta over 13 years ago in reply to Sobolevsky Vladik

TI__Intellectual 1915 points

Vladik,

I suspect that the M3 is running out of heap while allocating memory for VENC during the Loaded to Idle transition. Can you follow the instructions at http://processors.wiki.ti.com/index.php/OMX_Viewing_Media_Controller_Traces and share the loggerSM trace? It would help us to confirm the same.

Do you have the source code for M3? If it indeed turns out to be an insufficient heap size issue, you will require re-compilation of the M3 firmware to solve this issue for which source code will be required.

Regards,

Anirban