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Documentation of using TMS320C6678 cache

Jhon Scott
Intellectual 530 points
Other Parts Discussed in Thread: TMS320C6678

Hi, I actualy work as an intern in a company and I spent the whole day looking for some information about the cache memory in TMS320C6678.

In my internship, I have to send data in the L2 cache memory of one core and send an interruption to an other core to prevent him that it can read the data.

Here are my problems:

- I can't find the csl.h to include... I don't know what I have to do.. I use Sys Bios.

- I can't find any information or example on "how to configure" and "how to use" the cache memory on C6678.

Do you know where I can find some informations, or examples ?

Thank you.

  • 0
    TI__Mastermind 30825 points

    The cache details for the device are in the C66x Cache UG SPRUGY8 and the C66x CorePac UG SPRUGW0. That said, you don't send data from a Cache, you send data from a location, it may be cached but you still reference the location.  You need to understand the caching architecture, especially regarding coherency operations. 

    I'd also suggest starting with the example code in the MCSDK. http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide

    Best Regards,

    Chad