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GPMC FCLK

Michi Yama
Guru 10030 points

Hi,

Before, I asked " (1) Sync mode = 62.5MHz, Async mode=125MHz " in the note of Table 8-33 (page 241,datasheet sprs695a).

And I got some information from E2E that the correct is "sync mode=50MHz, Async mode=100MHz" and this frequency represents GPMC_FCLK.

However I am still confused.

According to TRM, it is written that GPMC_CLK is kept low when access is defined as asynchoronous.

Why async mode =100MHz is defined as the above? And why sync mode is the half frequency of async mode?

I must explain to customer the right meaning of this sentence.

Please give me some advice.

 

Best regards,

Michi 

  • 0
    TI__Prodigy 400 points

    Hello Michi,

    >>sync mode=50MHz, Async mode=100MHz" and this frequency represents GPMC_FCLK

    GPMC_FCLK is the functional clock on which all the internal transactions of GPMC work. Ex: Assertion/de-assertion of the other memory interface signals like ALE/OE/WE and others work on basis of their corresponding ontime/offtime programmed. The OE signal asserts at OEOntime and de-asserts at OEOfftime. The OEOntime,OEOfftime are programmed in terms of number of GPMC_FCLK cycles.

    >>According to TRM, it is written that GPMC_CLK is kept low when access is defined as asynchoronous.

    GPMC_CLK is the memory clock sent from GPMC to memory for having synchronous transfers between GPMC and memory. For thsi reason in asynchronous transfers GPMC_CLK is kept low.

    >>async mode =100MHz is defined as the above?

    as stated above this means that the internal transactions of GPMC work at GPMC_FCLK=100Mhz , while the memory interface clock GPMC_CLK=0. I.e. all the OE/WE/ALE assert and de-assert ( as programmed ) in multiples of 1/100MHz = multiples of 10ns.

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Dear Chaitanya-san,

    Thank you very much for your reply.

    I almost understood youre explanation. I appreciate your support.

    Then, I have one question.

    As you know, the frequency of GPMC_CLK is defined by CONFIG1_i register GPMCFCLKDIVIDER bit.

    This means the maximum frequency of GPMC_CLK is 100MHz with GPMCFCLKDIVIDER "00h" ( of course, this only synchronous mode).

    This means GPMC_FCLK is 100MHz at Synchronosu mode.  This is different from "sync mode=50MHz, Async mode=100MHz"

    The maximum frequency of GPMC_FLK at sync mode is 50MHz?  If it is so, I can understand the meaning  of  "sync mode=50MHz,

    Async mode=100MHz" sentence.   

    Please let me know.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Prodigy 400 points

    Hello Michi,

    Great point.Sorry that I missed this while giving my previous answer.

    Can you post the links of these two documents ( (i) data sheet       and       (ii)  E2E discussion).

    >>"sync mode=50MHz, Async mode=100MHz"

    I think the information this represents is as follows. This is neither specifically GPMC_FCLK nor GPMC_CLK.

    The frequency being talked here is the frequency of the clock using which the memory control signals are asserted/de-asserted.

    All the time GPMC works at GPMC_FCLK = 100MHz

    Asynchronous mode: All the Assert/de-assert are done with reference to  GPMC_FCLK = 100MHZ

    Synchronous mode:  All assertions/de-assertions are done with reference to GPMC_CLK = 100MHZ / ( 1+GPMCFCLKDIVIDER)

                   Normally in Synchronous mode GPMCFCLKDIVIDER = 0x1 ( GPMC_CLK = GPMC_FCLK/2 = 100MHz/2 = 50 Mhz)

    This seems to be the explanation for the statement. Please attach those two references in this forum thread.

    I will verify if this was what meant in the document.

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Chaitanya-san,

    Thank you for your reply.

    It was very cleared me.

    I posted the datasheet(P241)' snapshot the following.

     

     

     

     

  • 0 in reply to Michi Yama
    Guru 10030 points

    Chaitanya-san,

    Sorry for my mistake. I failed posting.

    I try again it.

    Please see the following.

    And, The link is the following.

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/183641/663907.aspx#663907

    Please verify it.

    Best regards,

    Michi

     

  • 0 in reply to Michi Yama
    TI__Prodigy 400 points

    Michi,

    This table by itself is not giving much information, but I understand that this table seems to be referring to a "Timing diagram" elsewhere.

    In such a case, my guess is correct.

    >>This is neither specifically GPMC_FCLK nor GPMC_CLK. The frequency being talked here is the frequency of the clock using which the memory control signals are asserted/de-asserted.

    >> All the time GPMC works at GPMC_FCLK = 100MHz

    >> Asynchronous mode: All the Assert/de-assert are done with reference to  GPMC_FCLK = 100MHZ

    >> Synchronous mode:  All assertions/de-assertions are done with reference to GPMC_CLK = 100MHZ / ( 1+ GPMCFCLKDIVIDER)

    >>               Normally in Synchronous mode GPMCFCLKDIVIDER = 0x1 ( GPMC_CLK = GPMC_FCLK/2 = 100MHz/2 = 50 Mhz)

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Dear, Chaitanya-san,

    Thank you for your re-confirmation.

    I appreciate your support.

    Best regards,

    Michi