Setting MC Shared Memory non cachable doesn't work

Hi,

It seems the addresses are not correctly coded. To obtain the same thing, that is in my case remapping 128K from 0x0C000000 to 0xF0000000, RW, I wrote:

XMAPX3_L = 0x00C000F6

XMAPX3_H= 0xF0000010

As per sprugw0a, para.7.3.1, logical RADDR (0xF0000000) bit31:8 must be written in MPAX_L bit 31:8, while the physical BADDR (0x0C000000) correspont to 0:0x0C000000 (the first zero is to identify the MCSM in the core internal 36bits addressing)

This is my (almost incomplete) routine:

struct pax_t{
  unsigned long low;
  unsigned long high;
};

#define PAX ((volatile struct pax_t*)0x08000000)

static void pax_remap(unsigned int priority, unsigned long virtual, unsigned long physical, unsigned long size_kbytes)
{
  const unsigned int perm=0xF6; //cannot execute  (0xFF=all permission)
  unsigned long size=size_kbytes>>2;
  unsigned int k=0x0A;
  for(; size; size=size>>1)
    ++k;
  unsigned long pax_h=virtual|k;
  unsigned long pax_l=0;
  if (physical>=0x80000000)
  {
    pax_l|=0x80000000;
    physical=physical & 0x0FFFFFFF;
  }
  pax_l=pax_l|(((physical>>12)<<8)|perm);

  PAX[priority].high=pax_h;
  PAX[priority].low=pax_l;
}

Hello Alberto,

thanks for your reply. I'm just reading once again the adress decoding to understand my mistakes. Beside this, I just typed a simple example with your configuration and also with enabling L1-cache on every core. Disable the cache direct works, mapping with MPAX doesn't work.

May you can try to execute my example? I suggest there's still a mistake in my configuration, but I'm unable to find something.

Best Regards,
Bernd

Hello together,

thanks for your suggestions and examples, I'll have a closer look at it on monday. But I've another question.

Maybe you can clarify the about address (de-) coding. I'm very confused about a lot of examples all doing not the same. Reading the CorePac UG I supposed that the BADDR is meant to be the Base address in the 32-Bit-CorePac Memory and the RADDR is meant to be the logical address in the 36-Bit-Physical Memory. But this isn't always in the examples, see below.

So the example from Alberto and also the example from the Software Transactional Memory is identical to the PDK-sample, this is consistent. But I wonder why the BADDR is related to address in the physical memory and the RADDR is related to the CorePac address. This isn't described in such a way in the CorePac UG.

Best Regards,
Bernd

---> 1) Sample from CorePac UserGuide Page 7-10 (Figure 7.7) <---
-Mapping 4 KB from Physical CorePac Address 0xC0007000 to 0x50042000
=> XMPAX-High: 0xC0007 | 00 | B
=> XMPAX-Low:  0x050042 | FF                              => Here everything is how I understood

---> 2) Sample from pdk_C6678_1_0_0_17\packages\ti\drv\cppi\example\sample\sample.c <---
-Mapping 1 MB from Physical CorePac Address 0x0C000000 to 0x81000000
=> XMPAX-High: 0x81000 | 0 | 13
=> XMPAX-Low:  0x00C000 | FF                              => Here the BADDR seems to be the Physical 36-Bit and the RADDR the CorePac 32-Bit

---> 3) Sample fromCCS5.1.1.00028\ccsv5\ccs_base\emulation\boards\evmc6678l\gel\evmc6678l.gel <---
=> XMPAX-High: 0x21000 | 00 | B
=> XMPAX-Low:  0x1000000 | FF
-This should do a mapping of 4 KB from ? to ?

---> 4) Example von Alberto <---
-Mapping 1 MB from Physical CorePac Address 0x0C000000 to 0xF0000000
=> XMPAX-High: 0xF0000 | 0 | 10
=> XMPAX-Low:  0x00C000 | F6                              => Here the BADDR seems to be the Physical 36-Bit and the RADDR the CorePac 32-Bit

Hello,

having read your examples tested your suggestions, everything works fine. Mistake was that the Shared memory has to be mapped into the mapped region; now the definitions (see below) works.

Now there's only the open question why the BADDR and RADDR are not used as defined in the UG (see example 1) in the note above), maybe you can clarify this issue.

Best Regards,
Bernd

#define XMC_BASE_ADDR (0x08000000)
#define MAPPED_VIRTUAL_ADDRESS  0x80000000
#define XMPAX3_L     (*(int*) (XMC_BASE_ADDR + 0x00000018))
#define XMPAX3_H     (*(int*) (XMC_BASE_ADDR + 0x0000001C))

    XMPAX3_H = 0x80000013;  // BADDR + segment size
    XMPAX3_L = 0x00C000FF;  // RADDR + permissions
    CACHE_setMemRegionInfo(128, 0, 0);

    OR

    CSL_XMC_XMPAXH mpaxh;
    CSL_XMC_XMPAXL mpaxl;

    // set shared l2 non-cacheable and non-prefetchable
    CACHE_setMemRegionInfo(128, 0, 0);
    mpaxh.segSize = 0x13;
    mpaxh.bAddr = 0x80000;
    mpaxl.ux = mpaxl.uw = mpaxl.ur = mpaxl.sx = mpaxl.sw = mpaxl.sr = 1;
    mpaxl.rAddr = 0x00C000;
    CSL_XMC_setXMPAXH(3, &mpaxh);
    CSL_XMC_setXMPAXL(3, &mpaxl);

I just wanted to second that Alberto's code example worked very well, together with Bernd's CACHE_setMemRegionInfo invocation, which, if placed within Alberto's function, would be invoked as:

CACHE_setMemRegionInfo(virtual >> 24, 0, 0)

I agree that the language in the manual is confusing. This discussion helped a lot.