• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 98 subscribers
  • Views 1118 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3874 GPMC_WAIT timing question (3)

Michi Yama
Guru 10030 points

Hi,

I have five question regarding GPMC_WAIT timing from my customer.

I attached excel file for my questions. Please see the attached file.

All questions are about GPMC_WAIT. The datasheet and TRM don't give enough information for me.

Please advise me.

Best regards,

Michi

6708.questions-GPMC_WAIT3.xlsx 

  • 0
    TI__Prodigy 400 points

    I  would prefer to answer your questions , a little out-of order.The diagram shows Asynchronous read from memory through GPMC.

    Back Ground of Asynncrhronous wait behavior.

    i) In Asynchronous mode, the memory does not take the clock input.

    i.e. in this mode, Memory to GPMC interface is an asynchronous interface.

    ii) Wait signal is an input to  GPMC given by Memory to indicates that certain internal events are yet to occur before it can read/write data.

    iii) GPMC does not "detect the WAIT" signal until the Accesstime, indicated in the diagram as "time A".  If at this time it finds WAIT is active, the data latch time is delayed.

    iv) In Asynchronous mode, after the WAIT signal is stable in ACTIVE/INACTIVE state, GPMC takes 2 or more FCLK cycles ( as per WAITMonitoringTime configuration) to "detect the WAIT". It is FCLK cycles because there is no interface of GPMC_CLK between GPMC and memory for Asynchronous transfers.

    >>(Q3) If  WAIT is  recognized at time"A",  is it allowed to de-assert WAIT at once?

    Wait is an input signal to GPMC given by the memory. Memory can de-assert the wait signal once

    memory does not deem it is necessary ( I.e. Memory is ready to take the write DATA).

    >>(Q4) If the cycle is extended  by WAIT assertion,  regarding time "A" and "B",  is this relation  always same?
    As stated in point  (iv) and (iii)  above, GPMC takes 2 or more FCLK cycles to detect the state of WAIT signal and when a WAIT signal is detected to be active the data is kept un-changed till it is detected to be inactive.

    So as the current gap between "A" and "B" is 2 or more FCLK cycles ( as per WAITMonitoringTime configuration). When  WAIT is extended by 'n' FCLK cycles by Memory, as many cycles the "A" and "B" will move apart.

    >>(Q2) If WAIT is already asserted in this timing,  is time "B" delayed each GPMC_FCLK(not GPMC_CLK) ?  
    Also I can't find the setup/hold time of WAIT to GPMC_FCLK  in the datasheet.

    As mentioned in (i) , there is no interface of GPMC_CLK between memory and GPMC in Asynchronous mode. So all the delays are calculated in GPMC_FCLK.

    The setup/hold time is not given because the memory by itself has no knowledge of GPMC_FCLK, so there is no specific setup/hold time that memory can follow w.r.t GPMC_FCLK. It is GPMC for its internal synchronization purpose that is uses GPMC_FCLK in asynchronous mode.

    >>(Q1) When  does Data0 be latched?  Is it time "B"? Also I can't find the setup /hold time of Data0 to GPMC_FCLK in the datasheet. Where can I find its spec?
    Data0 is latched  in "time B" . Again , since this is a Asynchronous read access, the Data is given by memory ( working asynchronous...) to GPMC ( which is working at GPMC_FCLK). So There is no setup/hold time of Data0 w.r.t GPMC_FLCK.

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    TI__Prodigy 400 points

    >>(Q5)  If WAIT is negated at the time "A" to "B" (two clock cycles before RDACCESSTIME completes,  is just only the latch timing  "B" delayed?
    Or is there any  problem?
     
    Rephrasing the question to check if I understood the question correctly::

        , If the Wait is made ACTIVE two cycles before the Access time "A" , does only the latch time "B" get delayed?

    YES.

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Chaitanya-san,

    Thank you for your support. Your answer is very helpful for me and my customer.

    I need your support little more.

    Regarding Q1,  I understood there is no setup/hold timing for Data0 to GPMC_FCLK.

    Customer asked me, "When does memory should  be valid the Data0?"

    I thnik  it is needed that the rising edge of WAIT signal(Inactive timing) and Data0 valid timing are the same time.

    Is my understandign right?

    Please let me know.

    Best regards,

    Michi   

  • 0 in reply to Michi Yama
    TI__Prodigy 400 points

    Not Sure If I understood your question correctly but,

    Normally the WAITmonitoringTime and AccessTime is set w.r.t the time when DATA0 ( coming from memory) gets valid

    Best regards,

    Chaitanya

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Chaitanya-san,

    Thank you for your reply.

    I understood your answer.

    User should set the WAITmonitoringTime and AccessTIme to be same as the time when DATA0 gets valid."

    By the way, please let me know the meaning " w.r.t " . I could not find it in my English dictionary.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    Guru 10030 points

    Chaitanya-san,

    Thank you for your support.

    I replied an answer to my customer based on your comment.

    However, custtomer doesn't satisfy to this answer. Customer would like to complete the cycle asap.

    Customer said the following.

               In asynchoronous mode,  it is very important that the relation between WAIT and Data.

               If external device is not memory, for example it is ASIC,  it is variable the valid timing of Data coming from external device.

               The cause of reason that it is not decided the timing of valid data is arbitration, interrupt and so on to the external device.

                So customer   needs the allowable time from WAIT deassertion to Data valid . Customer needs its allowable max value

                of the delay time between WAIT deassertion to data valid.

     

    Please give me more information about this issue.

     

    Best regards,

    Michi

     

  • 0 in reply to Michi Yama
    TI__Prodigy 400 points

    Michi,

    The behavior of Wait signal is such that: "The wait signal should be de-asserted WaitMonitoringTime+2 FCLK clock cycles before data is sampled"
    So Data Should be stable (WaitMonitoringTime+2)-1 data before wait de-asserts or in other words:

    Data should be given (WaitMonitoringTime+2)-1 FCLK clock cycles after WAIT de-assertion, and should be held same ( Hold time meeting) until (WaitMonitoringTime+2) + 1

    Best regards,

    Chaitanya

    post script:: "w.r.t" means "with reference to"

  • 0 in reply to Chaitanya Vaddadi
    Guru 10030 points

    Chaitanya-san,

    Thank you for your support.

    I talked with customer this point today.

    Customer suspects whether this is really proved or not. Could you verify it to your design engineer?

     Also, regarding your answer,

               Data should be given (WaitMonitoringTime+2)-1 FCLK clock cycles after WAIT de-assertion, and should be held same ( Hold time meeting) until                         (WaitMonitoringTime+2) + 1

     This sentece is represented " setup time is  Time B -1 FCLK,  and hold time is B+1 FCLK. Rgarding Time B, see the following.

    Then, customer would like to know the setup/hold time of WAIT to FCLK(Time "A").

    Could you give its information to me?

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Prodigy 400 points

    Michi,

    >> Could you verify it to your design engineer?

    I am the Design engineer for this module.

    >> The behavior of Wait signal is such that: "The wait signal should be de-asserted WaitMonitoringTime+2 FCLK clock cycles before data is sampled"

    This is the functionality of the WAIT signal. This is verified.

    >>   Data should be given (WaitMonitoringTime+2)-1 FCLK clock cycles after WAIT de-assertion, and should be held same ( Hold time meeting) until                         (WaitMonitoringTime+2) + 1

    >> This sentece is represented " setup time is  Time B -1 FCLK,  and hold time is B+1 FCLK.

    Firstly , this is a possible best practice I suggested to ensure setup and hold time for GPMC to sample memory data. This is not a rule documented  in any TRM or other spec.

    >> customer would like to know the setup/hold time of WAIT to FCLK

    Secondly as in Asynchronous mode, Memory does not receive any clock ( GPMC_CLK is kept low, GPMC_FCLK or GPMC_CLK is not visible to memory). So in Asynchronous mode, we cannot exactly mention any setup/hold times for WAIT with reference to GPMC_FCLK.

    Best regards,

    Chaitanya