Hello,
I'm using Starterware for C6748 1.20.02.02 and I'm overriding C6748.gel initialization for PLL and DDR with initialization functions PLL0Init() and PLL1Init() functions as seen in bl_am1808.c with the parameters seen below.
Running the OMAPL1x_debug.gel file tells me that PLL and DDR is correctly initialized, EMIFA interface, since is connected to PLL0_SYSCLK3, then that is 100MHz.
The problem is with an asynchronous device (AD7606) connected in parallel mode on EMA_CS4 as 16bit device (just like an SRAM) and instead of readings to happen in the ns range, the EMA_OE pin is active for like 1.14us (microseconds), this means readings are slow so something is wrong. The EMIFA asynchronous initialization for CS4 uses Read Setup time as 10ns, Read Strobe time as 20ns and Read Hold time as 10ns, tried with 1, 2, 1 but no change while reading.
Anyone has seen similar behaviour?
Reading is done as:
for(uint8_t i = 0; i < 4; i++)
{
m_iCh[i] = HWREG(SOC_EMIFA_CS4_ADDR);
}
PLL0 and PLL1 parameters:
PLL_CLK_SRC = 0
PLL0_MUL = 24
PLL0_PREDIV = 0
PLL0_POSTDIV = 1
PLL0_DIV1 = 0
PLL0_DIV3 = 2
PLL0_DIV7 = 5
/* Fixing PLL1 register values */
PLL1_MUL = 24
PLL1_POSTDIV = 1
PLL1_DIV1 = 0
PLL1_DIV2 = 1
PLL1_DIV3 = 2
This is the OMAPL1x_debug.gel output:
---------------------------------------------
C674X_0: GEL Output: | Device Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x0000000C
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5936977-11-29-38
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,6674
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0B02601D
C674X_0: GEL Output: DEV_INFO_25 = 0x005A9751
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x34240002
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | BOOTROM Info |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot Mode: SPI1 Flash
C674X_0: GEL Output:
ROM Status Code: 0x000000C4
Description:C674X_0: GEL Output: Error code not recognized
C674X_0: GEL Output:
Program Counter (PC) = 0x1182F3E4
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | Clock Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL0 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_PREDIV = 24 MHz
C674X_0: GEL Output: PLL0_PLLOUT = 600 MHz
C674X_0: GEL Output: PLL0_PLLOUT_POSTDIV = 300 MHz
C674X_0: GEL Output: PLL0_PLLEN = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL1 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
This is the code to initialize it:
#define NAND_WRITE_SETUP_TIME_IN_NS (0u)//0
#define NAND_WRITE_STROBE_TIME_IN_NS (0u)//tW(W)
#define NAND_WRITE_HOLD_TIME_IN_NS (0u)
#define NAND_READ_SETUP_TIME_IN_NS (10u)
#define NAND_READ_STROBE_TIME_IN_NS (20u)//tW(R)
#define NAND_READ_HOLD_TIME_IN_NS (10u)//0
#define NAND_TURN_ARND_TIME_IN_NS (0u)//0
void InitEMIFA()
{
PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_EMIFA, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
HWREG(SOC_EMIFA_0_REGS + EMIFA_NANDFCR) &= !EMIFA_NANDFCR_CS4NAND;//NOT using NAND on CS4
/* Set the Max extended wait cycles */ //shouldn't be needed
EMIFAMaxExtWaitCycleSet(SOC_EMIFA_0_REGS, NAND_MAX_EXT_WAIT);
/* Select pin0 to control external wait states. */
// EMIFACSWaitPinSelect(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_4, EMIFA_EMA_WAIT_PIN0);
/* set the polarity if EMA_WAIT[0] pin. */
// EMIFAWaitPinPolaritySet(SOC_EMIFA_0_REGS, EMIFA_EMA_WAIT_PIN0, EMIFA_EMA_WAIT_PIN_POLARITY_HIGH);
/* Disable the interrupts */
EMIFAMskedIntDisable(SOC_EMIFA_0_REGS, EMIFA_ASYNC_TIMOUT_INT);
EMIFAMskedIntDisable(SOC_EMIFA_0_REGS, EMIFA_LINE_TRAP_INT);
EMIFAMskedIntDisable(SOC_EMIFA_0_REGS, EMIFA_WAIT_RISE_INT);
/* Set the asynchronous wait timing */
uint32_t moduleClk = (NAND_MODULE_CLK / 1000000u); //EMIFA SYSCLK3
uint32_t wset = (((moduleClk * NAND_WRITE_SETUP_TIME_IN_NS)/1000u) &
EMIFA_WRITE_SETUP_RESETVAL);
uint32_t wstb = (((moduleClk * NAND_WRITE_STROBE_TIME_IN_NS)/1000u) &
EMIFA_WRITE_STROBE_RESETVAL);
uint32_t whld = (((moduleClk * NAND_WRITE_HOLD_TIME_IN_NS)/1000u) &
EMIFA_WRITE_HOLD_RESETVAL);
uint32_t rset = (((moduleClk * NAND_READ_SETUP_TIME_IN_NS)/1000u) &
EMIFA_READ_SETUP_RESETVAL);
uint32_t rstb = (((moduleClk * NAND_READ_STROBE_TIME_IN_NS)/1000u) &
EMIFA_READ_STROBE_RESETVAL);
uint32_t rhld = (((moduleClk * NAND_READ_HOLD_TIME_IN_NS)/1000u) &
EMIFA_READ_HOLD_RESETVAL);
uint32_t ta = (((moduleClk * NAND_TURN_ARND_TIME_IN_NS)/1000u) &
EMIFA_TA_RESETVAL);
uint32_t wtTimeConf = EMIFA_ASYNC_WAITTIME_CONFIG(wset, wstb, whld, rset, rstb, rhld,
ta);
EMIFAWaitTimingConfig(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_4, wtTimeConf);
/* Set the bus width */
EMIFAAsyncDevDataBusWidthSelect(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_4, EMIFA_DATA_BUSWITTH_16BIT);
EMIFAAsyncDevOpModeSelect(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_4, EMIFA_ASYNC_INTERFACE_NORMAL_MODE);
EMIFAExtendedWaitConfig(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_4, EMIFA_EXTENDED_WAIT_DISABLE);
}
Thank you for reading this post and hope anyone can help. Best regards,
David.
