Hello,
I’ve been doing some initial checkout on the McBSP port. I’ve been seeing some weird behavior that seems to be related the Frame Period (FPER) in the SRG. I am sending 16 bit words with a frame size of 1 word. The McBSP is the master and is generating the clock and frame signals. If I set FPER=17 or greater, then the port operates like I expect. If I set FPER=16 it seems like the McBSP sends each word twice. Is this an expected / known behavior? Or might I be doing something else wrong?
Below are my configuration settings for the port:
const mcbsp_hwcfg_t pxa320_ssp_cfg = {
.SPCR2 = MCBSP_SPCR2_FREE_DIS //Debugger options
| MCBSP_SPCR2_SOFT_EN,
.SPCR1 = MCBSP_SPCR1_ALB_DIS
| MCBSP_SPCR1_RJUST_RIGHT_ZERO
| MCBSP_SPCR1_DXENA_DIS,
.RCR2 = MCBSP_RCR2_RPHASE_SINGLE
| MCBSP_RCR2_RREVERSE_MSB_FIRST
| MCBSP_RCR2_RDATDLY_1,
.RCR1 = MCBSP_RCR1_RFRLEN1(1)
| MCBSP_RCR1_RWDLEN1_16,
.XCR2 = MCBSP_XCR2_XPHASE_SINGLE
| MCBSP_XCR2_XREVERSE_MSB_FIRST
| MCBSP_XCR2_XDATDLY_1,
.XCR1 = MCBSP_XCR1_XFRLEN1(1)
| MCBSP_XCR1_XWDLEN1_16,
.SRGR2 = MCBSP_SRGR2_GSYNC_FREE_RUN
| MCBSP_SRGR2_CLKSP_RISING
| MCBSP_SRGR2_CLKSM_0 //for clks
| MCBSP_SRGR2_FSGM_XB_FULL
| MCBSP_SRGR2_FPER(17),
.SRGR1 = MCBSP_SRGR1_FWID(1)
| MCBSP_SRGR1_CLKGDV(8), //96Mhz / 8 = 12Mhz
.PCR = MCBSP_PCR_SCLKME_0 //for clks
| MCBSP_PCR_FSXM_SRG
| MCBSP_PCR_FSRM_SRG
| MCBSP_PCR_CLKXM_OUT
| MCBSP_PCR_CLKRM_OUT
| MCBSP_PCR_FSXP_ACT_HIGH
| MCBSP_PCR_FSRP_ACT_HIGH
| MCBSP_PCR_CLKXP_RISING
| MCBSP_PCR_CLKRP_FALLING,
.SYSCONFIG = MCBSP_SYSCONFIG_CLOCKACTIVITY_ALL_OFF
| MCBSP_SYSCONFIG_SIDLEMODE_SMART
| MCBSP_SYSCONFIG_ENAWAKEUP_DIS,
.THRSH2 = MCBSP_THRSH2_XTHRESHOLD(1, MCBSP1345_THRSH_MASK),
.THRSH1 = MCBSP_THRSH1_RTHRESHOLD(1, MCBSP1345_THRSH_MASK),
.IRQENABLE = 0,
.WAKEUPEN = 0,
.XCCR = MCBSP_XCCR_EXTCLKGATE_DIS
| MCBSP_XCCR_PPCONNECT_EN
| MCBSP_XCCR_XHALF_CYCLE
| MCBSP_XCCR_XDMA_DIS,
.RCCR = MCBSP_RCCR_RHALF_CYCLE
| MCBSP_RCCR_RDMA_DIS,
};
Thanks!