TMS320C5505 Power Consumption - Lowest Power State

See this thread:

http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/110/t/117613.aspx

Yes, you need an RTC crystal and you need to shut off all of the internal power domains/clocks/PLL.

Hi Jeremy, Thanks for the reply. Can you be more specific when you say shut off the internal power domains? Are you simply referring to just the peripheral clock gating configuration register? 

Further, did you have any ideas on why I can't disable the master/system clock?

Thanks,

James,

I'm simply referring to the idle control register (ICR) and peripheral clock gating configuration registers (PCGCR1/2).

Regarding how to disable the master/system clock, I'll have my co-worker post a detailed response.  Standby.

-Jeremy

James,
Per the Errata:
When the master clock is disabled, there are no clocks for edge detection and therefore the INT0, INT1,
and WAKEUP pins are level-sensitive. This means that a low on either the INT0 or INT1 or a high on the
WAKEUP pin will force bit 15 of the PCGCR register to "0", enabling the master clock. Attempting to write
a "1" to bit 15 of the PCGCR register while INT0, INT1, or WAKEUP are asserted will be unsuccessful
since re-enabling the clocks has a higher priority than disabling them.

There are couple of things you should make sure you are doing.
If you are not using the WAKEUP pin, I would configure it as an output via the RTCPMGT register.

volatile ioport uint16_t * RTCPMGT = (volatile uint16_t *) 0x1930;
*RTCPMGT = 0x0008;

I am not sure what board you are using to test your code on, but if INTx lines aren't pulled up it won't disable the clock. One way to do this is to enable the Internal Pull Ups on those lines via Pull-Down Inhibit Register 2 (PDINHIBR2).

volatile ioport uint16_t * PDINHIBR2 = (volatile uint16_t *) 0x1C18;
*PDINHIBR2 &= ~(0x6000);

Cheers!

Hi Jrvanho,

Thank you very much for your detailed reply. 

I have seen some improvement in the power consumption when during the master clock off - indeed it was INT0 and INT1. 

However, the EMIF and IO supply bundles still draw 10mA. The ICR and RTCPMGT appear to have no affect on the consumption. 

The only drop in consumption is the master clock disable from the IDLE3 procedure. Do you have any further suggestions? The datasheet states <1mW when master clock is disabled. How do I get that?

All the best and thanks again for taking the time to help me out. 

James,

Have you confirmed that the USB oscillator is disabled?  I noticed that Jonathan's code, in the forum link I referenced above, explicitly disables the USB oscillator.  Perhaps it is enabled by the ROM bootloader.

James,

I would look at the code I posted at the link by Jeremy.  The code I wrote puts the processor in a really low power state with the exception of the INTx pull-up lines discussed above. If that doesn't seem to help any, please add more information; such as what board are you testing on, code, etc.

Cheers!

Hi, Thanks for getting back to me and for providing your suggestions.

The board is a bespoke board based on the ezDSP USB evaluation board. I have actually implemented the code linked by Jeremy on to an ezDSP USB board that I had and have verified (using measurements) that the DSP does draw <1mW. 

The same code is used to enter the bespoke board into low power mode but the DSP does not reduce its power consumption. 4.5mA is always drawn by the DVDDEMIF bundle. Note: the other supplies to reduce with the low power commands. On the evaluation board the EMIF current is 300uA always. 

My question is what on my bespoke board implementation is causing this extra 4.5mA? 

To help investigate, does this bundle only power the EMIF peripheral? The hardware layout for this peripheral is identical. From the datasheet table 3-8 EMIF terminal functions I have read "Note: This pin may consume static power if configured as Hi-Z and not pulled high or low. Prevent current drain by externally terminating the pin." Even though the eZDSP doesn't do this could this be the cause for the bespoke board?

The big difference between the ezDSP and the bespoke board is the use of the RTC: the ezDSP has one. Is the RTC interconnected with the EMIF supply somehow? I have read that some of the power management registers aren't available but I don't believe the linked code uses those registers. 

Thanks so much. 

It sounds like something is toggling or floating on the EMIF.

I can't tell which eZDSP you basing your design. If you are using the C5505, then it doesn't have anything connected to the EMIF except for GPIO[21:26], which can have internal pull-ups enabled. If you are using the C5515, that does have external Flash attached. From the boards I have played around with I haven't seen a need for pull-ups, but they are always a good idea esp. on the data lines. Are you using SDRAM?

Does your bespoke board not use the RTC? How is it wired up? If it is not hooked up, did you follow the RTC app note?

If the RTC is not used, CVDDRTC and DVDDRTC must still be supplied because internal signals
from the RTC are required for operation of the DSP's Power On Reset circuitry. In addition,
the RTC_XI pin must be tied to CVDDRTC and the RTC_XO pin must be tied to VSS. If the
RTC_XI and RTC_XO pins are tied off, then the RTC registers are not accessible.

If you aren't using the 32 kHz crystal, are you using a 12 MHz clock? If so, this might increase current draw.

Have you tested this on several of your boards? If so, do you see the same behavior?

Sorry I can't help more without the schematics and such. These are just some thoughts.

Cheers!

Hi Jrvanho,

Thanks for your further suggestions. Though I beleived I had tried this before, I have now managed to reduce the current drawn by the EMIF supplies.

For some reason 5mA is drawn when the multiplexed GPIO/EMIF pins are set as GPIO - enough though they are inputs. Setting them to EMIF reduced the current to 0.

Thanks for all the support.