Hello,
I am using dma sample program located at http://processors.wiki.ti.com/index.php/Programming_EDMA_without_EDMA3LLD_package
I have modified registers in this code for omap3 platform to use QDMA.
I want to dma 80 bytes from src to dst using 2D dma.
Here is snippet of the code.
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SRC = (unsigned int)(srcBuff);
A_B_CNT = ((10 << 16u) | (8 & 0xFFFFu)); /* ACNT = 8, BCNT = 10 */
DST = (unsigned int)(dstBuff);
SRC_DST_BIDX = (32 << 16u) | (32 & 0xFFFFu); /* SRC_BIDX = 32, DST_BIDX = 32 for example; since it is 2D to 2D transfer, DST_BIDX = stride set by user ,write to destination buffer in 2D */
LINK_BCNTRLD = (1 << 16u) | 0xFFFFu; /* LINK = 0xFFFF, BCNTRLD = 1 */
SRC_DST_CIDX = 0;
CCNT = 1;
/* Step 3: Triggering the Transfer and Waiting for Transfer Completion */
while(((IPR) & 0x1) == 0);
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When I measure dma completion cycles i.e dma wait cycles across while statement (above line) in CCSV5, cycles required to perform DMA are observed to be 1472 cycles.
When I modify code to transfer 4KB of data, cycles required are observed to be 7280 cycles.
I think these are very high numbers.
Are cycle numbers like this expected?
Thanks in advance.
Regards,
Mike