c6678 assembly

The interrupt will not be dropped, but it will not be taken during the execution of the short loop.  Basically, it cannot take an interrupt during the delay slots of a branch, doing so would result in the CorePac jumping back to wherever that branch was going to go.  So a short loop (i.e. 5 cycle or less) will prevent an interrupt from being taken while in the loop.  That said, the interrupt event still stays active and will be taken as soon as you leave the loop (i.e. as soon as you're not in the delay slots of a branch.)

For more details please see chapter 6 of the C66x CPU and Instruction UG - SPRUGH7.

Best Regards,
Chad

hello:

 below is my assembly code,   Need I disable interrupt before loop kernel , and enable interrupt after loop kernel?

thanks!
                                     .global _CplxMulCplx
_CplxMulCplx:

mv b6, b0 ;b0 = N
|| mv a4, a22 ;a22 = X = a0
|| mv a6, a23 ;a23 = Z = a3
|| mv b4, b22 ;b22 = Y
mv b3, a14
mv a6, b3
|| zero a1
|| zero b1
shru b0, 2, b0 ;b0*2/8
sub b0,2, b0 
sub b0, 2, b0 

lddw *b22++, a29:a28 ;a28 = pX[i+2], a29 = pX[i+3]
lddw *a22++, a31:a30 ;a30 = pX[i] real; a31 = pX[i+1] imag

lddw *a22++, b31:b30 ;b30 = pY[i] real; b31 = pY[i+1] imag
lddw *b22++, b29:b28 ;b28 = pY[i+2], b29 = pY[i+3]

lddw *b22++, a25:a24 ;a24 = pX[i+6], a25 = pX[i+7]
lddw *a22++, a27:a26 ;a26 = pX[i+4], a27 = pX[i+5]

lddw *a22++, b27:b26 ;b26 = pY[i+4], b27 = pY[i+5]
|| cmpysp a31:a30, a29:a28, a19:a18:a17:a16 ;1
lddw *b22++, b25:b24 ;b24 = pY[i+6], b25 = pY[i+7]

cmpysp b31:b30, b29:b28, b19:b18:b17:b16 ;2
|| lddw *b22++, a29:a28

lddw *a22++, a31:a30

cmpysp a27:a26, a25:a24, a7:a6:a5:a4 ;3
|| daddsp a19:a18, a17:a16, a21:a20 ;1
|| lddw *a22++, b31:b30

lddw *b22++, b29:b28

cmpysp b27:b26, b25:b24, b7:b6:b5:b4 ;4
|| daddsp b19:b18, b17:b16, b21:b20 ;2
|| lddw *b22++, a25:a24

fsubsp b1, a21, b2 ;1
|| lddw *a22++, a27:a26

daddsp a7:a6, a5:a4, a11:a10 ;3
|| mv a20, b9 ;1
|| lddw *a22++, b27:b26 ;b26 = pY[i+4], b27 = pY[i+5]
|| cmpysp a31:a30, a29:a28, a19:a18:a17:a16 ;1

fsubsp a1, b21, a2 ;2
|| lddw *b22++, b25:b24

;loop kernel

loop:
daddsp b7:b6, b5:b4, b11:b10 ;4
|| mv b2, b8 ;1
|| mv b20, a13
|| cmpysp b31:b30, b29:b28, b19:b18:b17:b16 ;2
|| lddw *b22++, a29:a28

stdw b9:b8, *b3++
|| fsubsp b1, a11, b2 ;3
|| addk 8, a23
|| lddw *a22++, a31:a30

mv a2, a12 ;2
|| mv a10, b9
|| bdec loop,b0
|| cmpysp a27:a26, a25:a24, a7:a6:a5:a4 ;3
|| daddsp a19:a18, a17:a16, a21:a20 ;1
|| lddw *a22++, b31:b30

stdw a13:a12, *a23++
|| fsubsp a1, b11, a2 ;4
|| addk 8, b3
|| lddw *b22++, b29:b28

mv b2, b8 ;3
|| mv b10, a13
|| cmpysp b27:b26, b25:b24, b7:b6:b5:b4 ;4
|| daddsp b19:b18, b17:b16, b21:b20 ;2
|| lddw *b22++, a25:a24

stdw b9:b8, *b3++
|| addk 8, a23
|| fsubsp b1, a21, b2 ;1
|| lddw *a22++, a27:a26

mv a2, a12 ;4
|| daddsp a7:a6, a5:a4, a11:a10 ;3
|| mv a20, b9 ;1
|| lddw *a22++, b27:b26 ;b26 = pY[i+4], b27 = pY[i+5]
|| cmpysp a31:a30, a29:a28, a19:a18:a17:a16 ;1

stdw a13:a12, *a23++
|| addk 8, b3
|| fsubsp a1, b21, a2 ;2
|| lddw *b22++, b25:b24

;LOOP EPILOG
daddsp b7:b6, b5:b4, b11:b10 ;4
|| mv b2, b8 ;1
|| mv b20, a13
|| cmpysp b31:b30, b29:b28, b19:b18:b17:b16 ;2

stdw b9:b8, *b3++
|| fsubsp b1, a11, b2 ;3
|| addk 8, a23

mv a2, a12 ;2
|| mv a10, b9
|| cmpysp a27:a26, a25:a24, a7:a6:a5:a4 ;3
|| daddsp a19:a18, a17:a16, a21:a20 ;1

stdw a13:a12, *a23++
|| fsubsp a1, b11, a2 ;4
|| addk 8, b3

mv b2, b8 ;3
|| mv b10, a13
|| cmpysp b27:b26, b25:b24, b7:b6:b5:b4 ;4
|| daddsp b19:b18, b17:b16, b21:b20 ;2

stdw b9:b8, *b3++
|| addk 8, a23
|| fsubsp b1, a21, b2 ;1

mv a2, a12 ;4
|| daddsp a7:a6, a5:a4, a11:a10 ;3
|| mv a20, b9 ;1

stdw a13:a12, *a23++
|| addk 8, b3
|| fsubsp a1, b21, a2 ;2

daddsp b7:b6, b5:b4, b11:b10 ;4
|| mv b2, b8 ;1
|| mv b20, a13

stdw b9:b8, *b3++
|| fsubsp b1, a11, b2 ;3
|| addk 8, a23

mv a2, a12 ;2
|| mv a10, b9

stdw a13:a12, *a23++
|| fsubsp a1, b11, a2 ;4
|| addk 8, b3

mv b2, b8 ;3
|| mv b10, a13

stdw b9:b8, *b3++
|| addk 8, a23

mv a2, a12 ;4

stdw a13:a12, *a23++
|| addk 8, b3

;结束
mv a14, b3
b b3
nop 5

Hello Chad,

You say that the interrupt will not be dropped, but it will be taken as soon as the loop execution is finished.

Now, let us assume that the pipelined loop takes some time so that I receive another interrupt from the same source. Then what happens? Will the ISR connected to that interrupt be executed twice or just once? Does this situation differ wheteher the interrupt source is HW or SW, meaning HWI or SWI?

Supposing that my ISR is executed only once, so this means that I missed the previous interrupt. Then what to do?

Thank you,

Abdulkerim

Chad Courtney said:

No, the only time you need to manually disable / enable interrupts is around ISR's.  This is done automatically if you use C to create your ISR's (interrupt service routines) and follow the instructions on how to create them.

This is like worst country song ever :-) "Around ISR"? "Done automatically if you use C to create your ISR's"? "Do not need to disable interrupts except for when creating an ISR"? No, no and no. If we talk about ISR, then if anything needs to be done about disabling/enabling interrupts, then it's specifically in ISR, not "around". ISR's are entered with interrupts disabled, but it has nothing to do with compiler. In fact C compiler is not in position to determine where or not interrupts can be enabled in ISR, ISR programmer is. As result compiler does exactly nothing about enabling/disabling interrupts in ISR, it's explicit programmer's responsibility. But as far as I can tell question is not about ISR at all...

At the same time it should be noted that not all question are fair. One can not count on arbitrary, overly specific question to be directly answered. This is because specific aspects of specific code can be prohibitively hard to figure out. For example in this case question if interrupts need to be disabled can't be answered without deep understanding of algorithm and more importantly implementation itself. In extreme cases it might be easier for non-author to provide own implementation than to answer overly specific question about somebody else's one. What TI can and should do in such situation is to explain under which conditions interrupts would have to be disabled (yes,there are conditions even for plain, non-ISR code, after all, even compiler uses it occasionally, yes, even in non-ISR context), so that OP can judge whether or not it's the case for him-/herself. Yes, there are cases when interrupts are disabled implicitly (as correctly mentioned  for example in branch delay slots, SPLOOP is another example), but it doesn't change the principle that you have to recognize circumstances when they have to be disabled. Whether or not it happens implicitly or explicitly is implementation question, not principle.