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saLoopBackFbDev crashes

_Ralph_
Guru 10685 points
Other Parts Discussed in Thread: TVP7002

I am having trouble running saLoopBackFbDev.

I have patched my video driver files as per this post:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/160009.aspx

in order to capture video without the TVP7002 (I just have an FPGA feeding 1080p60 RGB 24bit video into VIN on the DM8168).

The output of what I am seeing is below. Please could someone from TI help me get this working?

Thanks,

Ralph

# /usr/local/share/ti/ti-media-controller-utils/load-hd-v4l2-firmware.sh start
Loading HDVICP2 Firmware
DM816X prcm_config_app version: 2.0.0.1
Doing PRCM settings...
        PRCM for IVHD0 is in Progress, Please wait.....
                        BW Phy Addr : 0x48180600 Data : 0x00000002
                        AW Phy Addr : 0x48180600 Data : 0x00000002
                        Phy Addr : 0x48180c04 Data : 0x00000037
                        BW Phy Addr : 0x48180620 Data : 0x00070000
                        AW Phy Addr : 0x48180620 Data : 0x00070002
                        BW Phy Addr : 0x48180624 Data : 0x00030000
                        AW Phy Addr : 0x48180624 Data : 0x00010002
                        Phy Addr : 0x48180600 Data : 0x00000102
                        BW Phy Addr : 0x48180c10 Data : 0x00000007
                        AW Phy Addr : 0x48180c10 Data : 0x00000003
                        Phy Addr : 0x48180c14 Data : 0x00000004
                        BW Phy Addr : 0x58088000 Data : 0x19a08500
                        AW Phy Addr : 0x58088000 Data : 0xeafffffe
                        BW Phy Addr : 0x58098000 Data : 0xf0b48835
                        AW Phy Addr : 0x58098000 Data : 0xeafffffe
                        BW Phy Addr : 0x48180c10 Data : 0x00000003
                        AW Phy Addr : 0x48180c10 Data : 0x00000000
                        Phy Addr : 0x48180c14 Data : 0x00000007
        PRCM for IVHD0 is Done Successfully
        PRCM for IVHD1 is in Progress, Please wait.....
                        BW Phy Addr : 0x48180700 Data : 0x00000002
                        AW Phy Addr : 0x48180700 Data : 0x00000002
                        Phy Addr : 0x48180d04 Data : 0x00000037
                        BW Phy Addr : 0x48180720 Data : 0x00070000
                        AW Phy Addr : 0x48180720 Data : 0x00050002
                        BW Phy Addr : 0x48180724 Data : 0x00030000
                        AW Phy Addr : 0x48180724 Data : 0x00010002
                        Phy Addr : 0x48180700 Data : 0x00000102
                        BW Phy Addr : 0x48180d10 Data : 0x00000007
                        AW Phy Addr : 0x48180d10 Data : 0x00000003
                        Phy Addr : 0x48180d14 Data : 0x00000004
                        BW Phy Addr : 0x5a088000 Data : 0xd499f25b
                        AW Phy Addr : 0x5a088000 Data : 0xeafffffe
                        BW Phy Addr : 0x5a098000 Data : 0x8f9f0190
                        AW Phy Addr : 0x5a098000 Data : 0xeafffffe
                        BW Phy Addr : 0x48SysLink version : 2.10.03.20
SysLink module created on Date:May 15 2012 Time:18:49:50
180d10 Data : 0x00000003
                        AW Phy Addr : 0x48180d10 Data : 0x00000000
                        Phy Addr : 0x48180d14 Data : 0x00000007
        PRCM for IVHD1 is Done Successfully
        PRCM for IVHD2 is in Progress, Please wait.....
                        BW Phy Addr : 0x48180800 Data : 0x00000002
                        AW Phy Addr : 0x48180800 Data : 0x00000002
                        Phy Addr : 0x48180e04 Data : 0x00000037
                        BW Phy Addr : 0x48180820 Data : 0x00070000
                        AW Phy Addr : 0x48180820 Data : 0x00050002
                        BW Phy Addr : 0x48180824 Data : 0x00030000
                        AW Phy Addr : 0x48180824 Data : 0x00010002
                        Phy Addr : 0x48180800 Data : 0x00000102
                        BW Phy Addr : 0x48180e10 Data : 0x00000007
                        AW Phy Addr : 0x48180e10 Data : 0x00000003
                        Phy Addr : 0x48180e14 Data : 0x00000004
                        BW Phy Addr : 0x53088000 Data : 0xbd1e6562
                        AW Phy Addr : 0x53088000 Data : 0xeafffffe
                        BW Phy Addr : 0x53098000 Data : 0x5f67bf87
                        AW Phy Addr : 0x53098000 Data : 0xeafffffe
                        BW Phy Addr : 0x48180e10 Data : 0x00000003
                        AW Phy Addr : 0x48180e10 Data : 0x00000000
                        Phy Addr : 0x48180e14 Data : 0x00000007
        PRCM for IVHD2 is Done Successfully
PRCM Initialization completed
FIRMWARE: I2cInit will be done by M3
FIRMWARE: Memory map bin file not passed
Usage : firmware_loader <Processor Id> <Location of Firmware> <start|stop> [-mmap <memory_map_file>] [-i2c <0|1>]
===Mandatory arguments===
<Processor Id>         0: DSP, 1: Video-M3, 2: Vpss-M3
<Location of Firmware> firmware binary file
<start|stop>           to start/stop the firmware
===Optional arguments===
-mmap                  input memory map bin file name
-i2c                   0: i2c init not done by M3, 1(default): i2c init done by M3
FIRMWARE: isI2cInitRequiredOnM3: 1
FIRMWARE: Default memory configuration is used
MemCfg: DCMM (Dynamically Configurable Memory Map) Version :  2.1.2.1
FIRMWARE: Memory Configuration status : In Progress
FIRMWARE: 1 start Successful
Loading HDVPSS (V4L2) Firmware
FIRMWARE: I2cInit will be done by M3
FIRMWARE: Memory map bin file not passed
Usage : firmware_loader <Processor Id> <Location of Firmware> <start|stop> [-mmap <memory_map_file>] [-i2c <0|1>]
===Mandatory arguments===
<Processor Id>         0: DSP, 1: Video-M3, 2: Vpss-M3
<Location of Firmware> firmware binary file
<start|stop>           to start/stop the firmware
===Optional arguments===
-mmap                  input memory map bin file name
-i2c                   0: i2c init not done by M3, 1(default): i2c init done by M3
FIRMWARE: isI2cInitRequiredOnM3: 1
FIRMWARE: Default memory configuration is used
MemCfg: DCMM (Dynamically Configurable Memory Map) Version :  2.1.2.1
FIRMWARE: Memory Configuration status : In Progress
FIRMWARE: 2 start Successful
ti81xxvin ti81xxvin: TI81xx HDVPSS Capture driver initialized
HDMI W1 rev 2.0
*************Bodge 1 enabled to turn on DVI regardless of what is attached.
# /usr/clockchip
I2C opened okay.
Written configuration.
Finished setting clocks.
# /usr/saLoopBackFbdev
Driver Name: ti81xxvin
Driver bus info: TI81xx Platform
DriverSection 1
 is capable of dSection 2
oing capture
saLoopBackFbdev:
 Mode set is 0
*************Bodge 1 enabled to turn on DVI regardless of what is attached.
I2C Bus Low?

=============================================================
Capture Format:
=============================================================
fmt.type                 = 1
fmt.width                = 1920
fmt.height               = 1080
fmt.pixelformat  = 859981650
fmt.bytesperline         = 5760
fmt.sizeimage    = 6220800
=============================================================

Fix Screen Info:
----------------
Line Length - 7680
Physical Address = b0b00000
Buffer Length = 41943040

Var Screen Info:
----------------
Xres - 1920
Yres - 1080
Xres Virtual - 1920
Y------------[ cut here ]------------
WARNING: at kernel/softirq.c:159 local_bh_enable+0x54/0xd4()
Modules linked in: ti81xxhdmi ti81xxvin ti81xxvo ti81xxfb vpss syslink
Backtrace:
[<c0317f1c>] (dump_backtrace+0x0/0x110) from [<c05ffd7c>] (dump_stack+0x18/0x1c)
 r7:00000000 r6:c03420dc r5:c06af304 r4:0000009f
[<c05ffd64>] (dump_stack+0x0/0x1c) from [<c033c294>] (warn_slowpath_common+0x54/0x6c)
[<c033c240>] (warn_slowpath_common+0x0/0x6c) from [<c033c2d0>] (warn_slowpath_null+0x24/0x2c)
 r9:c0748e44 r8:d7084780 r7:0000000d r6:d53f6500 r5:c0726260
r4:c076f740
[<c033c2ac>] (warn_slowpath_null+0x0/0x2c) from [<c03420dc>] (local_bh_enable+0x54/0xd4)
[<c0342088>] (local_bh_enable+0x0/0xd4) from [<c033524c>] (omap_mbox_msg_send+0xdc/0xec)
 r5:c0726260 r4:00000000
[<c0335170>] (omap_mbox_msg_send+0x0/0xec) from [<c055de54>] (notify_shm_drv_send_event+0x1c8/0x208)
 r5:00000001 r4:00000000
[<c055dc8c>] (notify_shm_drv_send_event+0x0/0x208) from [<c055b5e4>] (notify_send_event+0x114/0x26c)
[<c055b4d0>] (notify_send_event+0x0/0x26c) from [<bf11e914>] (vps_fvid2_queue+0xe4/0x21c [vpss])
[<bf11e830>] (vps_fvid2_queue+0x0/0x21c [vpss]) from [<bf127ac8>] (capture_queue+0x50/0x64 [vpss])
 r8:bf14fed4 r7:60000013 r6:d5365c80 r5:00000000 r4:d55d2400
[<bf127a78>] (capture_queue+0x0/0x64 [vpss]) from [<bf14ed3c>] (ti81xxvin_buffer_queue+0x9c/0xe8 [ti81xxvin])
 r5:d55d3800 r4:d55d2400
[<bf14eca0>] (ti81xxvin_buffer_queue+0x0/0xe8 [ti81xxvin]) from [<c0539938>] (videobuf_streamon+0x88/0xfc)
 r7:60000013 r6:d55d3904 r5:d55d39c4 r4:d5365c80
[<c05398b0>] (videobuf_streamon+0x0/0xfc) from [<bf14e804>] (vidioc_streamon+0x1c4/0x330 [ti81xxvin])
 r7:d55d3904 r6:00000001 r5:d55d3800 r4:00000000
[<bf14e640>] (vidioc_streamon+0x0/0x330 [ti81xxvin]) from [<c052ef48>] (__video_do_ioctl+0x1618/0x3f34)
 r7:d55f7000 r6:40045612 r5:00000000 r4:00000001
[<c052d930>] (__video_do_ioctl+0x0/0x3f34) from [<c052d720>] (__video_usercopy+0x2e4/0x428)
[<c052d43c>] (__video_usercopy+0x0/0x428) from [<c052d894>] (video_ioctl2+0x30/0x38)
[<c052d864>] (video_ioctl2+0x0/0x38) from [<c052c8d4>] (v4l2_ioctl+0xe8/0x11c)
 r5:d55f7000 r4:d535a280
[<c052c7ec>] (v4l2_ioctl+0x0/0x11c) from [<c03abbbc>] (vfs_ioctl+0x28/0x44)
 r9:d5628000 r8:be8adc44 r7:00000004 r6:00000004 r5:d535a280
r4:d54d37e0
[<c03abb94>] (vfs_ioctl+0x0/0x44) from [<c03ac350>] (do_vfs_ioctl+0x558/0x5a0)
[<c03abdf8>] (do_vfs_ioctl+0x0/0x5a0) from [<c03ac3f0>] (sys_ioctl+0x58/0x7c)
[<c03ac398>] (sys_ioctl+0x0/0x7c) from [<c03146e0>] (ret_fast_syscall+0x0/0x30)
 r8:c0314864 r7:00000036 r6:00000001 r5:00000004 r4:00012168
---[ end trace 6d5e0088fd309320 ]---
BUG: scheduling while atomic: saLoopBackFbdev/691/0x00000002
Modules linked in: ti81xxhdmi ti81xxvin ti81xxvo ti81xxfb vpss syslink
Backtrace:
[<c0317f1c>] (dump_backtrace+0x0/0x110) from [<c05ffd7c>] (dump_stack+0x18/0x1c)
 r7:d5629ae8 r6:00000000 r5:d50dd340 r4:00000000
[<c05ffd64>] (dump_stack+0x0/0x1c) from [<c0336c2c>] (__schedule_bug+0x54/0x60)
[<c0336bd8>] (__schedule_bug+0x0/0x60) from [<c06000c4>] (schedule+0x78/0x3c0)
 r5:d50dd340 r4:00030d40
[<c060004c>] (schedule+0x0/0x3c0) from [<c0601610>] (schedule_hrtimeout_range_clock+0x148/0x188)
[<c06014c8>] (schedule_hrtimeout_range_clock+0x0/0x188) from [<c0601664>] (schedule_hrtimeout_range+0x14/0x18)
[<c0601650>] (schedule_hrtimeout_range+0x0/0x18) from [<c03476d8>] (usleep_range+0x4c/0x54)
[<c034768c>] (usleep_range+0x0/0x54) from [<bf11e950>] (vps_fvid2_queue+0x120/0x21c [vpss])
 r5:d53e7580 r4:d5629b90
[<bf11e830>] (vps_fvid2_queue+0x0/0x21c [vpss]) from [<bf127ac8>] (capture_queue+0x50/0x64 [vpss])
 r8:bf14fed4 r7:60000013 r6:d5253580 r5:00000001 r4:d55d2400
[<bf127a78>] (capture_queue+0x0/0x64 [vpss]) from [<bf14ed3c>] (ti81xxvin_buffer_queue+0x9c/0xe8 [ti81xxvin])
 r5:d55d3800 r4:d55d2400
[<bf14eca0>] (ti81xxvin_buffer_queue+0x0/0xe8 [ti81xxvin]) from [<c0539938>] (videobuf_streamon+0x88/0xfc)
 r7:60000013 r6:d55d3904 r5:d55d39c4 r4:d5253580
[<c05398b0>] (videobuf_streamon+0x0/0xfc) from [<bf14e804>] (vidioc_streamon+0x1c4/0x330 [ti81xxvin])
 r7:d55d3904 r6:00000001 r5:d55d3800 r4:00000000
[<bf14e640>] (vidioc_streamon+0x0/0x330 [ti81xxvin]) from [<c052ef48>] (__video_do_ioctl+0x1618/0x3f34)
 r7:d55f7000 r6:40045612 r5:00000000 r4:00000001
[<c052d930>] (__video_do_ioctl+0x0/0x3f34) from [<c052d720>] (__video_usercopy+0x2e4/0x428)
[<c052d43c>] (__video_usercopy+0x0/0x428) from [<c052d894>] (video_ioctl2+0x30/0x38)
[<c052d864>] (video_ioctl2+0x0/0x38) from [<c052c8d4>] (v4l2_ioctl+0xe8/0x11c)
 r5:d55f7000 r4:d535a280
[<c052c7ec>] (v4l2_ioctl+0x0/0x11c) from [<c03abbbc>] (vfs_ioctl+0x28/0x44)
 r9:d5628000 r8:be8adc44 r7:00000004 r6:00000004 r5:d535a280
r4:d54d37e0
[<c03abb94>] (vfs_ioctl+0x0/0x44) from [<c03ac350>] (do_vfs_ioctl+0x558/0x5a0)
[<c03abdf8>] (do_vfs_ioctl+0x0/0x5a0) from [<c03ac3f0>] (sys_ioctl+0x58/0x7c)
[<c03ac398>] (sys_ioctl+0x0/0x7c) from [<c03146e0>] (ret_fast_syscall+0x0/0x30)
 r8:c0314864 r7:00000036 r6:00000001 r5:00000004 r4:00012168
res Virtual - 1080
nonstd       - 0
Bits Per Pixel - 32
blue lenth 8 msb 0 ofBUG: scheduling while atomic: saLoopBackFbdev/691/0x00000002
fset 0
red lentModules linked in:h 8 msb 0 offset ti81xxhdmi 16
green lenth ti81xxvin 8 msb 0 offset  ti81xxvo8
trans lenth 8 ti81xxfb msb 0 offset 24 vpss

Var Screen I syslinknfo:
----------
------
Xres - 1Backtrace: 920
Yres - 1080

Xres Virtual -[<c0317f1c>] (dump_backtrace+0x0/0x110) from [<c05ffd7c>] (dump_stack+0x18/0x1c)
 1920
Yres Virt r7:d5629ae8ual - 4320
nons r6:00000000td       - 0
Bi r5:d50dd340ts Per Pixel - 2 r4:000000004
blue lenth 8
msb 0 offset 0
[<c05ffd64>] (dump_stack+0x0/0x1c) from [<c0336c2c>] (__schedule_bug+0x54/0x60)
red lenth 8 msb [<c0336bd8>] (__schedule_bug+0x0/0x60) from [<c06000c4>] (schedule+0x78/0x3c0)
0 offset 16
gre r5:d50dd340en lenth 8 msb 0 r4:00030d40 offset 8
trans
 lenth 0 msb 0 o[<c060004c>] (schedule+0x0/0x3c0) from [<c0601610>] (schedule_hrtimeout_range_clock+0x148/0x188)
ffset 0

Fix S[<c06014c8>] (schedule_hrtimeout_range_clock+0x0/0x188) from [<c0601664>] (schedule_hrtimeout_range+0x14/0x18)
creen Info:
---[<c0601650>] (schedule_hrtimeout_range+0x0/0x18) from [<c03476d8>] (usleep_range+0x4c/0x54)
-------------
L[<c034768c>] (usleep_range+0x0/0x54) from [<bf11e950>] (vps_fvid2_queue+0x120/0x21c [vpss])
ine Length - 576 r5:d53e75800
Physical Addr r4:d5629b90ess = b0b00000

Buffer Length = [<bf11e830>] (vps_fvid2_queue+0x0/0x21c [vpss]) from [<bf127ac8>] (capture_queue+0x50/0x64 [vpss])
41943040
 r8:bf14fed4 r7:60000013 r6:d52da000 r5:00000002 r4:d55d2400
[<bf127a78>] (capture_queue+0x0/0x64 [vpss]) from [<bf14ed3c>] (ti81xxvin_buffer_queue+0x9c/0xe8 [ti81xxvin])
 r5:d55d3800 r4:d55d2400
[<bf14eca0>] (ti81xxvin_buffer_queue+0x0/0xe8 [ti81xxvin]) from [<c0539938>] (videobuf_streamon+0x88/0xfc)
 r7:60000013 r6:d55d3904 r5:d55d39c4 r4:d52da000
[<c05398b0>] (videobuf_streamon+0x0/0xfc) from [<bf14e804>] (vidioc_streamon+0x1c4/0x330 [ti81xxvin])
 r7:d55d3904 r6:00000001 r5:d55d3800 r4:00000000
[<bf14e640>] (vidioc_streamon+0x0/0x330 [ti81xxvin]) from [<c052ef48>] (__video_do_ioctl+0x1618/0x3f34)
 r7:d55f7000 r6:40045612 r5:00000000 r4:00000001
[<c052d930>] (__video_do_ioctl+0x0/0x3f34) from [<c052d720>] (__video_usercopy+0x2e4/0x428)
[<c052d43c>] (__video_usercopy+0x0/0x428) from [<c052d894>] (video_ioctl2+0x30/0x38)
[<c052d864>] (video_ioctl2+0x0/0x38) from [<c052c8d4>] (v4l2_ioctl+0xe8/0x11c)
 r5:d55f7000 r4:d535a280
[<c052c7ec>] (v4l2_ioctl+0x0/0x11c) from [<c03abbbc>] (vfs_ioctl+0x28/0x44)
 r9:d5628000 r8:be8adc44 r7:00000004 r6:00000004 r5:d535a280
r4:d54d37e0
[<c03abb94>] (vfs_ioctl+0x0/0x44) from [<c03ac350>] (do_vfs_ioctl+0x558/0x5a0)
[<c03abdf8>] (do_vfs_ioctl+0x0/0x5a0) from [<c03ac3f0>] (sys_ioctl+0x58/0x7c)
[<c03ac398>] (sys_ioctl+0x0/0x7c) from [<c03146e0>] (ret_fast_syscall+0x0/0x30)
 r8:c0314864 r7:00000036 r6:00000001 r5:00000004 r4:00012168
BUG: scheduling while atomic: saLoopBackFbdev/691/0x00000002
Modules linked in: ti81xxhdmi ti81xxvin ti81xxvo ti81xxfb vpss syslink
Backtrace:
[<c0317f1c>] (dump_backtrace+0x0/0x110) from [<c05ffd7c>] (dump_stack+0x18/0x1c)
 r7:d5629ae8 r6:00000000 r5:d50dd340 r4:00000000
[<c05ffd64>] (dump_stack+0x0/0x1c) from [<c0336c2c>] (__schedule_bug+0x54/0x60)
[<c0336bd8>] (__schedule_bug+0x0/0x60) from [<c06000c4>] (schedule+0x78/0x3c0)
 r5:d50dd340 r4:00030d40
[<c060004c>] (schedule+0x0/0x3c0) from [<c0601610>] (schedule_hrtimeout_range_clock+0x148/0x188)
[<c06014c8>] (schedule_hrtimeout_range_clock+0x0/0x188) from [<c0601664>] (schedule_hrtimeout_range+0x14/0x18)
[<c0601650>] (schedule_hrtimeout_range+0x0/0x18) from [<c03476d8>] (usleep_range+0x4c/0x54)
[<c034768c>] (usleep_range+0x0/0x54) from [<bf11e950>] (vps_fvid2_queue+0x120/0x21c [vpss])
 r5:d53e7580 r4:d5629b90
[<bf11e830>] (vps_fvid2_queue+0x0/0x21c [vpss]) from [<bf127ac8>] (capture_queue+0x50/0x64 [vpss])
 r8:bf14fed4 r7:60000013 r6:d5491480 r5:00000003 r4:d55d2400
[<bf127a78>] (capture_queue+0x0/0x64 [vpss]) from [<bf14ed3c>] (ti81xxvin_buffer_queue+0x9c/0xe8 [ti81xxvin])
 r5:d55d3800 r4:d55d2400
[<bf14eca0>] (ti81xxvin_buffer_queue+0x0/0xe8 [ti81xxvin]) from [<c0539938>] (videobuf_streamon+0x88/0xfc)
 r7:60000013 r6:d55d3904 r5:d55d39c4 r4:d5491480
[<c05398b0>] (videobuf_streamon+0x0/0xfc) from [<bf14e804>] (vidioc_streamon+0x1c4/0x330 [ti81xxvin])
 r7:d55d3904 r6:00000001 r5:d55d3800 r4:00000000
[<bf14e640>] (vidioc_streamon+0x0/0x330 [ti81xxvin]) from [<c052ef48>] (__video_do_ioctl+0x1618/0x3f34)
 r7:d55f7000 r6:40045612 r5:00000000 r4:00000001
[<c052d930>] (__video_do_ioctl+0x0/0x3f34) from [<c052d720>] (__video_usercopy+0x2e4/0x428)
[<c052d43c>] (__video_usercopy+0x0/0x428) from [<c052d894>] (video_ioctl2+0x30/0x38)
[<c052d864>] (video_ioctl2+0x0/0x38) from [<c052c8d4>] (v4l2_ioctl+0xe8/0x11c)
 r5:d55f7000 r4:d535a280
[<c052c7ec>] (v4l2_ioctl+0x0/0x11c) from [<c03abbbc>] (vfs_ioctl+0x28/0x44)
 r9:d5628000 r8:be8adc44 r7:00000004 r6:00000004 r5:d535a280
r4:d54d37e0
[<c03abb94>] (vfs_ioctl+0x0/0x44) from [<c03ac350>] (do_vfs_ioctl+0x558/0x5a0)
[<c03abdf8>] (do_vfs_ioctl+0x0/0x5a0) from [<c03ac3f0>] (sys_ioctl+0x58/0x7c)
[<c03ac398>] (sys_ioctl+0x0/0x7c) from [<c03146e0>] (ret_fast_syscall+0x0/0x30)
 r8:c0314864 r7:00000036 r6:00000001 r5:00000004 r4:00012168


  • 0
    Guru 10685 points

    I should have also pointed out that I am not using embedded sync in my RGB signal into the DM8168 (not sure how this is possible anyway with RGB).

    I don't have the tvp7002 module loaded.

    Attached are my modified ti81xx_vpss.c and ti81xxvin_main.c files.

    Thanks,
    Ralph

    3644.ti81xxvin_main.c

    Fullscreen 0383.ti81xx_vpss.c Download 
    /*
 *
 * Framebuffer device registration for TI TI816x platforms
 *
 * Copyright (C) 2009 Texas Instruments Inc.
 * Author: Yihe Hu <yihehu@ti.com>
 *
 * Some code and ideas taken from TI OMAP2 Platforms
 * by Tomi Valkeinen.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/bootmem.h>
#include <linux/io.h>
#include <linux/vps_capture.h>
#include <linux/ti81xxfb.h>
#include <linux/ti81xx.h>
#include <mach/hardware.h>
#include <mach/board-ti814x.h>
#include <mach/board-ti816x.h>
#include <asm/mach/map.h>


#if defined(CONFIG_TI81XX_VPSS) || defined(CONFIG_TI81XX_VPSS_MODULE)

static u64 ti81xx_dma_mask = ~(u32)0;
static struct platform_device vpss_device = {
	.name = "vpss",
	.id = -1,
	.dev = {
		.platform_data = NULL,
	},
};
static struct vps_platform_data vps_pdata;


static int __init ti81xx_vpss_init(void)
{
	/*FIXME add platform data here*/
	int r;
	if (cpu_is_ti816x() || cpu_is_dm385()) {
		if (cpu_is_dm385())
			vps_pdata.cpu = CPU_DM813X;
		else
			vps_pdata.cpu = CPU_DM816X;
		vps_pdata.numvencs = 4;
		vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1;
	} else if (cpu_is_ti814x()) {
		vps_pdata.cpu = CPU_DM814X;
		vps_pdata.numvencs = 3;
		vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1 \
					- VPS_DC_VENC_HDCOMP;
	}

	vpss_device.dev.platform_data = &vps_pdata;
	r = platform_device_register(&vpss_device);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_vpss device\n");
	else
		printk(KERN_INFO "registered ti81xx_vpss device\n");
	return r;
}

#if defined(CONFIG_TI81XX_HDMI_MODULE) || defined(CONFIG_TI81XX_HDMI)

static struct platform_device ti81xx_hdmi_plat_device = {
	.name = "TI81XX_HDMI",
	.id = -1,
	.num_resources = 0,
	.dev = {
		/*.release = ti81xx_hdmi_platform_release,*/
		.platform_data = NULL,
	}
};

static int __init ti81xx_hdmi_init(void)
{
	int r;
	/*FIXME add platform data here*/
	r = platform_device_register(&ti81xx_hdmi_plat_device);
	if (r)
		printk(KERN_ERR "Unable to register ti81xx onchip-HDMI device\n");
	else
		printk(KERN_INFO "registered ti81xx on-chip HDMI device\n");
	return r;
}
#else
static int __init ti81xx_hdmi_init(void)
{
	return 0;
}
#endif

#if defined(CONFIG_VIDEO_TI81XX_VIDIN_MODULE) || \
		defined(CONFIG_VIDEO_TI81XX_VIDIN)

#define HDVPSS_CAPTURE_INST0_BASE	0x48105500
#define HDVPSS_CAPTURE_INST0_SIZE	1024u

#define HDVPSS_CAPTURE_INST2_BASE	0x48105A00
#define HDVPSS_CAPTURE_INST2_SIZE	1024u
u8 ti81xx_card_name[] = "TI81xx_catalogue";
struct ti81xxvin_interface tvp7002_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 0,
	.vs_polarity = 1,
	.fid_polarity = 0,
	.sog_polarity = 0,

};
static struct ti81xxvin_subdev_info hdvpss_capture_sdev_info[] = {
	{
		.name	= TVP7002_INST0,
		.board_info = {
			/* TODO Find the correct address
				of the TVP7002 connected */
			I2C_BOARD_INFO("tvp7002", 0x5d),
			.platform_data = &tvp7002_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
		.input_data_format = FVID2_DF_YUV422P,
	},
	{
		.name	= TVP7002_INST1,
		.board_info = {
			I2C_BOARD_INFO("tvp7002", 0x5c),
			.platform_data = &tvp7002_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
		.input_data_format = FVID2_DF_YUV422P,
	},
};

static const struct v4l2_dv_preset hdvpss_inst0_inp0_presets[] = {
	{
		.preset = V4L2_DV_720P60,
	},
	{
		.preset = V4L2_DV_1080I60,
	},
	{
		.preset = V4L2_DV_1080P60,
	},
	{
		.preset = V4L2_DV_1080P30,
	},
};

static const struct v4l2_dv_preset hdvpss_inst2_inp0_presets[] = {
	{
		.preset = V4L2_DV_720P60,
	},
	{
		.preset = V4L2_DV_1080I60,
	},
	{
		.preset = V4L2_DV_1080P60,
	},
	{
		.preset = V4L2_DV_1080P30,
	},
};

static const struct ti81xxvin_input hdvpss_inst0_inputs[] = {
	{
		.input = {
			.index		= 0,
			.name		= "Component",
			.type		= V4L2_INPUT_TYPE_CAMERA,
			.std		= V4L2_STD_UNKNOWN,
			.capabilities	= V4L2_OUT_CAP_PRESETS,
		},
		.subdev_name	= TVP7002_INST0,
		.dv_presets	= hdvpss_inst0_inp0_presets,
		.num_dv_presets	= ARRAY_SIZE(hdvpss_inst0_inp0_presets),
	},
};

static const struct ti81xxvin_input hdvpss_inst1_inputs[] = {
	{
		.input = {
			.index		= 0,
			.name		= "Component",
			.type		= V4L2_INPUT_TYPE_CAMERA,
			.std		= V4L2_STD_UNKNOWN,
			.capabilities	= V4L2_OUT_CAP_PRESETS,
		},
		.subdev_name	= TVP7002_INST1,
		.dv_presets	= hdvpss_inst2_inp0_presets,
		.num_dv_presets	= ARRAY_SIZE(hdvpss_inst2_inp0_presets),
	},
};

/* 16 bit decoders are present on the Port A of VIP0 and VIP1 instances. Which
represents the VIP0 and VIP2 instances in software. While Port B of VIP0 and
VIP1 are represented by VIP1 and VIP3 instances. On these two instances no
decoders are present.
*/
static struct ti81xxvin_config ti81xx_hsvpss_capture_cfg = {
	.subdev_info = hdvpss_capture_sdev_info,
	.subdev_count = ARRAY_SIZE(hdvpss_capture_sdev_info),
	.card_name = ti81xx_card_name,
	.inst_config[0] = {
		.inputs = hdvpss_inst0_inputs,
		.input_count = ARRAY_SIZE(hdvpss_inst0_inputs),
	},
	.inst_config[1] = {
		.inputs = hdvpss_inst0_inputs,
		.input_count = 0,
	},
	.inst_config[2] = {
		.inputs = hdvpss_inst1_inputs,
		.input_count = ARRAY_SIZE(hdvpss_inst1_inputs),
	},
	.inst_config[3] = {
		.inputs = hdvpss_inst1_inputs,
		.input_count = 0,
	},

};

static struct resource ti81xx_hdvpss_capture_resource[] = {
	[0] = {
		.start = HDVPSS_CAPTURE_INST0_BASE,
		.end   = (HDVPSS_CAPTURE_INST0_BASE +
				HDVPSS_CAPTURE_INST0_SIZE - 1),
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = HDVPSS_CAPTURE_INST2_BASE,
		.end   = (HDVPSS_CAPTURE_INST2_BASE +
				HDVPSS_CAPTURE_INST2_SIZE - 1),
		.flags = IORESOURCE_MEM,
	},
};

static struct platform_device hdvpss_capture_dev = {
	.name		= "ti81xxvin",
	.id		= -1,
	.dev		= {
			.dma_mask		= &ti81xx_dma_mask,
			.coherent_dma_mask	= ~(u32)0,
	},
	.num_resources = 2,
	.resource = ti81xx_hdvpss_capture_resource,
};

static int __init ti81xx_vin_init(void)
{
	int r;
	printk("ti81xx_vin_init modded by Ralph.\n");
	
	hdvpss_capture_dev.dev.platform_data = &ti81xx_hsvpss_capture_cfg;
	if (cpu_is_ti814x()) {
		hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder =
			vps_ti814x_select_video_decoder;
		hdvpss_capture_sdev_info[0].ti81xxvin_set_mode =
			vps_ti814x_set_tvp7002_filter;
		hdvpss_capture_sdev_info[0].decoder_id = 0;
		hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder =
			NULL;
		hdvpss_capture_sdev_info[1].ti81xxvin_set_mode =
			NULL;
		hdvpss_capture_sdev_info[1].decoder_id = 0;
	} 
// Altered by Ralph
	else {
		hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder =
			//vps_ti816x_select_video_decoder;	// contains an i2c call "i2c_transfer(pcf8575_2_client->adapter, &msg, 1)"
			NULL;
		hdvpss_capture_sdev_info[0].ti81xxvin_set_mode =
			//vps_ti816x_set_tvp7002_filter;	// Does bugger all anyway.
			NULL;
		hdvpss_capture_sdev_info[0].decoder_id = 0;
		hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder =
			NULL;
		hdvpss_capture_sdev_info[1].ti81xxvin_set_mode =
			NULL;
		hdvpss_capture_sdev_info[1].decoder_id = 0;
	}
	r = platform_device_register(&hdvpss_capture_dev);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_vin device\n");
	else
		printk(KERN_INFO "registered ti81xx_vin device\n");
	return r;

}
#else
static int __init ti81xx_vin_init(void)
{
	return 0;
}

#endif

#if defined(CONFIG_FB_TI81XX_MODULE) || defined(CONFIG_FB_TI81XX)
static struct ti81xxfb_platform_data ti81xxfb_config;

static struct platform_device ti81xx_fb_device = {
	.name		= "ti81xxfb",
	.id		= -1,
	.dev = {
		.dma_mask		= &ti81xx_dma_mask,
		.coherent_dma_mask	= ~(u32)0,
		.platform_data		= &ti81xxfb_config,
	},
	.num_resources = 0,
};


void ti81xxfb_set_platform_data(struct ti81xxfb_platform_data *data)
{
	ti81xxfb_config = *data;
}

static int __init ti81xx_fb_init(void)
{
	int r;
	r = platform_device_register(&ti81xx_fb_device);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_fb device\n");
	else
		printk(KERN_INFO "registered ti81xx_fb device\n");
	return r;

}
#else
static int __init ti81xx_fb_init(void)
{
	return 0;
}
void ti81xxfb_set_platform_data(struct ti81xxfb_platform_data *data)
{
}
#endif

#if defined(CONFIG_VIDEO_TI81XX_VIDOUT_MODULE) || \
		defined(CONFIG_VIDEO_TI81XX_VIDOUT)
static struct resource ti81xx_vidout_resource[VPS_DISPLAY_INST_MAX] = {
};

static struct platform_device ti81xx_vidout_device = {
	.name		= "t81xx_vidout",
	.num_resources  = ARRAY_SIZE(ti81xx_vidout_resource),
	.resource       = &ti81xx_vidout_resource[0],
	.id             = -1,
};

static int __init ti81xx_init_vout(void)
{
	int r;

	r = platform_device_register(&ti81xx_vidout_device);
	if (r)
		printk(KERN_ERR "Unable to register ti81xx_vidout device\n");
	else
		printk(KERN_INFO "registered ti81xx_vidout device\n");
	return r;
}
#else
static int __init ti81xx_init_vout(void)
{
	return 0;
}
#endif


static int __init ti81xx_init_vpss(void)
{
	int retval = 0;
	/*if vpss failed to register, none of the below could works*/
	if (ti81xx_vpss_init())
		return -1;
	retval = ti81xx_init_vout();
	retval += ti81xx_hdmi_init();
	retval += ti81xx_fb_init();
	retval += ti81xx_vin_init();
	return retval;
}

arch_initcall(ti81xx_init_vpss);

#endif

  • 0 in reply to _Ralph_
    Guru 10685 points

    I have this fixed now.

    After applying TI's 5 patches from here, commenting out the subdev calls, and setting up hdvpss_capture_sdev_info correctly in ti81xx_vpss.c and setting ti81xxvin_select_decoder fields of hdvpss_capture_sdev_info to NULL the application no longer crashes and the dumped data is making sense.

    Only issue now is to persuade fbdev to actually display on video out.

    Ralph

  • 0 in reply to _Ralph_
    TI__Mastermind 20245 points

    Hi,

    Good to know. Are you seeing kernel dumps now while capture is started first time. This should be solved after applying patches. Please let me know observation.

    Regards,

    Hardik Shah

  • 0 in reply to _Ralph_
    TI__Mastermind 20245 points

    Hi,

    what do you mean here by

    _Ralph_ said:
    Only issue now is to persuade fbdev to actually display on video out.

    I am not getting above question.

    Regards,

    Hardik Shah

  • 0 in reply to HardikShah
    Guru 10685 points

    Hi Hardik,

    There are indeed no more crashes now that I've applied the patches you posted on the forum.

    The saLoopBackFbdev demo does not seem to output any video. Should it be doing this?

    In addition, the capture_encode demo (OpenMAX) does not output video, only a white screen. I have modified it so that the setup of the TVP control component is skipped entirely. Is it possible to persuade the HDVICPs to output in DVI format in the same way that I have persuaded the VPSS driver to do so in dctrl.c (in dc_timing_to_device_timing)?

    Thanks,

    Ralph

  • 0 in reply to _Ralph_
    TI__Mastermind 20245 points

    Hi,

    I am not getting below question.

    _Ralph_ said:
    Is it possible to persuade the HDVICPs to output in DVI format in the same way that I have persuaded the VPSS driver to do so in dctrl.c

    Regards,

    Hardik Shah

  • 0 in reply to HardikShah
    Guru 10685 points

    Okay, perhaps it's best just to focus on one thing at a time. Do you know why the saLoopBackFbdev demo is not displaying any video on screen?

    Thanks,
    Ralph