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GPMC_WAIT questions (4)

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Hi,

I have questions regarding GPMC_WAIT.

I made excel sheet for questions.

Please see the attached file, and give me answers for my customer.

I appreciate your quick reply.

Best regards,

Michi

4478.questions-GPMC_WAIT4.xlsx

  • 0
    TI__Prodigy 400 points

    Hello Michi

    >> Q1 >> I would like to reconfirm . Second  GPMC_WAIT signal can assert  as soon as previous GPMC _WAIT  signal  deassertion, can't it?

    Yes, but it needs at least one clock cycle gap ( GPMC_FCLK for Asynchronous transfers and GPMC_CLK for synchronous transfers). this allows GPMC to sample the WAIT inactive window.

    >> Q2 >> On burst mode, the WAIT  must  be satisfied WAITMONITORINGTIME  for D0. But  how about D1, D2, D3? Does not the WAIT  need to satisfy the  WAITMONITORINGTIME  for  D1, D2, D3?  

    I am not sure if I understood this question clearly. Did you mean:

    If Wait was de-asserted for D0 and immediately after 1 cycle asserted itself, then even for D1 ( or similarly for D2,D3) WAIT needs to satisfy WAITMONITORINGTIME ?

    Yes this is true.

    >> Q3 >> Is this possible, such as the red line's WAIT signal.

    Yes this is possible.

    >> Q4 >> According to the data sheet(Fig 8-21 to Fig. 8-26),  the assertion of GPMC_WAIT signal  is doen when GPMC_ADV_ALE signal is low.  Is there any timing requirement between GPMC_WAIT and GPMC_ADV_ALE?

    The WAIT signal is given by the memory, the memory can give a wait signal earliest when the memory detects the request for an access.

    In Synchronous memory access, the memory samples the address bus on the first rising clock edge when the GPMC_ADV_ALE signal is asserted. For this reason the timing diagram shows the memory asserting GPMC_WAIT signal asserting after the first rising edge when the GPMC_ADV_ALE signal is asserted.

    >> Q5 >> I was advised WAIT signal toggle in WAIT inactive period is not effect, but it is not recommended.      
        According to the additional information, customer would like to use one WAIT pin for multiple CS
        (Customer would like to use both Asynchronous I/F and Synchronous I/F each CS(Chip Select) with one WAIT pin).  
        Can TI guarantee the GPMC of AM3874 with this use?

    I am not clear on how you are relating the first point in this question to the others. But.

    Same WAIT signal can be used by different CS, Asynchronous/Synchronous does not matter. But you have below limitations:

       1) cannot expect different WAITPINPOLARITY for different CS.

       2) Normally at the reset phase, the "GPMC_STATUS.WAITXStatus" register bits are read to see the status of WAIT signal coming from memory,You need to ensure by how to read WAIT pin status of two memories are connected to same WAIT pin.

    Best regards,

    Chaitanya