• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 418 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Accessing the cache memory in omap4430 !!!

studinstru sggs
Expert 2335 points


Hi,

I want to access the omap4430 cache memory (32kb :I && 32kb : D cache).

How i will access this memory through instructions or code ?????

-Studinstru

  • 0
    TI__Prodigy 390 points

    Cortex A9 Cache memory(both L1D and L1P) is not addressable. So you cannot read the contents of the cache memory.

     

    You can only turn on the caches and you should see a visible improvement in your performance. If you are using Linux or Android, then you can be assured, that these caches are already getting enabled somewhere. If you are trying to run ARM-BIOS or some OS like that on Cortex A9, you may have to call some specific API to enable it.

  • 0 in reply to Ranjith Parakkal
    Expert 2335 points

    Thanks Ranjith.

    Can u give more explanation on linux based platform...?

    such that which api to use......etc..

    your guidance will definitely help me

    -studinstru

  • 0 in reply to studinstru sggs
    TI__Prodigy 390 points

    On Linux there are no cache related APIs available on the user side. The cache would be getting set somewhere in the kernel during boot-up time.  I dont know the exact APIs. But you can be sure that on OMAP4 data cache and instruction cache are already getting set in Linux. However there are some memory regions like tiler buffers where data caching is disabled.

     

    What exactly is your usecase. Why do you need cache APIs ? That will help me answer you better.