Hi
In TRM 24.3.2.10: "The McSPI controller has a built-in FFNBYTE bytes buffer in order to unload DMA or interrupt handler and improve data throughput. The use of this buffer is optional and depends on a generic parameter USEFIFO. The FIFO is enabled when it is set to 1. Allowed FIFO depth up to 64 bytes is supported and is defined by generic parameter FFNBYTE."
How can I configure these generic parameters, USEFIFO and FFNBYTE? I did not find any register documented in TRM to do it.
Looking at source code, I see that MLO/U-boot enables FFEW and FFWR bits in MCSPI_CH(i)CONF register but I did not find any configuration of MCSPI_XFERLEVEL, nor MCSPI_DAFTX and MCSPI_DAFRX registers are used anywhere. Is it enough to enable FIFO usage or not?
On the other hand Linux driver code do not set FFEW and FFWR bits.
Any clarification will be appreciated, thanks.
Best regards,
Max
