Other Parts Discussed in Thread: OMAPL138, OMAP-L138
I have a question regarding the timing of the uPP clock, start, enable and data signals. The uPP User's Guide (Literature Number SPRUGJ5B) makes a vague statement in section 2.5.6 that I would like help clarifying. See the snippet below
"The uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals align on the rising edge of CLOCK, but its polarity is controlled by the CLKINVx bit in UPICR. The active edge(s) of CLOCK should always slightly precede transitions of other uPP signals. "
I'm confused by the last sentence. I have a FPGA transmitting data to the OMAPL138 via the uPP. How should I interpret "The active edge of CLOCK should always slightly preceded transitions of other uPP signals". How much time satisfies a "slight" amount? Is there another document I'm missing with electrical timing specifications?
Thanks for your time,
Dave M.
