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Where can I find a diagram which depicts the system clock distribution? The am3517 trm does not have it

mrunmoy samal
Prodigy 90 points
Other Parts Discussed in Thread: AM3517

Hi,

I am looking for a simple clock distribution diagram to understand how the input clock is distributed to various peripherals, dplls, mpu core. I am not able to locate such a figure in the am3517 TRM. Could anyone point me to the same.

Attaching a sample diagram for the same which shows what I am looking for.

Thanks,

Mrunmoy

  • 0
    TI__Expert 6655 points

    Hi Samal,

    You can refer "4.7 PRCM Clock Manager Functional Description" section in TRM http://www.ti.com/litv/pdf/sprugr0b

    Regards

    AnilKumar

    Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

  • 0 in reply to Anil
    Prodigy 90 points

    That is exactly what I was looking for, I guess I didn't look well enough into the TRM.

    Thanks a lot Anil.

    - Mrunmoy

  • 0 in reply to mrunmoy samal
    Prodigy 90 points

    I have one more question. I read through the clock module but I could not figure out what is the value of SYS_CLK. The TRM says that there is a divider between OSC_SYS_CLK and SYS_CLK but does not say which register sets the divider value. The figure below shows the hardware configuration of our system and I need to figure out what is the value of SYS_CLK.

    Although the PRM_CLKSEL register points something about the OSC_SYS_CLK, but my sys_xtalin is already connected to 26Mhz. What happens to the OSC_SYS_CLK if the below register is not configured to the only available value of 0x3???

    Below, its mentioned that the SYS_CLK is OSC_SYS_CLK divided by 2. Is it always divided by two? or can we chose the divisor? if Yes, which register lets us choose the divisor?