What to do after disabling DDR2 VCLK?

Hi,

Among the methods to save L138’s external DDR2 and DDR2 controller power, section 15.2.16.1 of SPRUH77 advised also turning off VCLK.

However, VCLK ultimately comes from PLL0_SYSCLK2(/2), as can be seen from

• Section 15.2.16
• Figure 7-3

Then there seems to be a big problem. In section 7.1, table 7-2, PLL0_SYSCLK2 is listed as must having fixed ½ ratio to PLL0_SYSCLK1, and what is more important, it clocks ARM RAM and shared RAM. This means that if VCLK were to be shut, so it PLL0_SYSCLK2, and it will both

1. Violate the fixed ratio with PLL0_SYSCLK1
2. Shut ARM RAM and shared RAM

And the only place ARM is still able to execute code should be the DSP RAM, which AMR shall access through DSP megamodule’s S(slave)DMA (see table 4-1 system interconnect matrix, of SPRUH77).

Then in this situation, if we still want to use ARM, we cannot make DSP sleep since ARM requires RAM in DSP’s megamodule; or if we just sleep ARM and uses DSP solely.

Is this the case?

Paul