Hello. If anyone has any experience with this I'd love to get some pointers. I need to configure the high frequency AUXCLK for master operation. Basically I need to run as an I2S master using the internal high frequency clock. By default it seems to be running at 20 MHz which doesn't divide down nicely to audio bit rates.
I'm a little confused by the McASP driver configuration for DIT mode. It sets the high frequency divider to a single value (register AHCLKXCTL field HCLKXDIV set to 3), then the code comment declares: "Only 44100 and 48000 are valid, both have the same setting". Presumably then the PLL must be configured to different values to yield an appropriate bit clock frequency but I can't find where this might be done.
Any suggestions or pointers to relevant documentation would be appreciated.