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McASP master clock configuration (Linux)

Hello. If anyone has any experience with this I'd love to get some pointers. I need to configure the high frequency AUXCLK for master operation. Basically I need to run as an I2S master using the internal high frequency clock. By default it seems to be running at 20 MHz which doesn't divide down nicely to audio bit rates.

I'm a little confused by the McASP driver configuration for DIT mode. It sets the  high frequency divider to a single value (register AHCLKXCTL field HCLKXDIV set to 3), then the code comment declares: "Only 44100 and 48000 are valid, both have the same setting". Presumably then the PLL must be configured to different values to yield an appropriate bit clock frequency but I can't find where this might be done.

 Any suggestions or pointers to relevant documentation would be appreciated.

  • In case anyone else needs to do this. For me the solution was to use the functions declared in include/linux/clk.h to mux the clocks (the platform board setup code looks like a good place to do this). The architecture specific implementation is also useful as a reference for how to effectively alter some of the lower level parameters.

  • Hello Przemyslaw,

    Can you give more input? I'm trying to output a 48KHz signal. So far, I've only been able to generate a 52KHz. Thank you for your input.

    Kefil

  • I think I was mainly focused on how to manipulate the clock select multiplexers above.

    I'm running on the TI814x EVM. There is a 24.576 MHz clock available on the board that's perfect for these frequencies (including 48kHz), but by default it's only connected to the Audio codec. It's generated by U43 if you want to find it on the schematics. You can connect it to the CPU by loading the appropriate resistor(s) and then the clock signal is available on XREF1 - XREF3 (depending on the resistor connected).

    If this isn't an option for you then you might try the Audio PLLs to generate an appropriate clock. The clock signal won't be as clean but it might not matter for audio frequencies anyway. I haven't had a need to do this though so I won't be able to help you with the PLLs.

  • Hi Przemyslaw ,

    Based on your suggestion, I install an external oscillator of 24.576Mhz contected to Aud_Clk_In2. I'm trying to find a way to make it work. Do you know how to setup the McAsp2 to use this new external clock?

    Thank you!

    Kefil

  • This is actually kind of tricky to do with McASP2. I haven't found a way to connect any of the XREF clocks to the AUXCLK inputs on McASP0 - McASP2. You have two options. If the AHCLKX_IN input is sufficient you can still do this, although I expect for audio frequencies that won't suffice. Alternatively you can use McASP3 - McASP5 and then it's easy.

    To connect (multiplex) AUD_CLKIN2 to the AUXCLK input on McASP3 you would do something like this (I'm assuming you're working with Linux):

    struct clk *xref_clk2, *mcasp3_auxclk;

    xref_clk2 = clk_get_sys(NULL, "xref2_ck");
    mcasp3_auxclk = clk_get_sys("davinci-mcasp.3", NULL);

    clk_set_parent(mcasp3_auxclk, xref_clk2);

    /* clean up */
    clk_put(xref_clk2);
    clk_put(mcasp3_auxclk);

    Make sure you do the appropriate error handling for those calls as well. If you would like to connect to  AHCLKX_IN on McASP2, instead of the mcasp3_auxclk reference we got above, you will need to get the following clock instead (the number 3 is not a mistake here):

    mcasp2_ahclkx_in = clk_get_sys(NULL, "mcasp3_ahx_ck");

    One last thing. Before multiplexing the clock signals with clk_set_parent(), you will need to tell the system what clock rate the XREF clock is actually running at, as this information will also be propagated and may be used by some parts of the system. You do it like this:

    xref_clk2->rate = 24576000;
    propagate_rate(xref_clk2);

    Hope that gets you on the right path.

  • Thank you for your help Przemyslaw!

    I've been able to succesfully get audio @48kHz using McAsp2. I apply these changes:

        clkp = clk_get(NULL,"mcasp3_ahx_ck");
        if(!clkp) printk("mcasp3_ahx_ck\n");
        else printk("mcasp3_ahx_ck successed.\n");

        new_parent = clk_get(NULL,"xref2_ck");
        if(!new_parent) printk("xref2_ck failed\n");
        else printk("xref2_ck get successed.\n");

       clk_set_parent(clkp, new_parent);

    mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);