Hello,
I am unable to configure the C6455 McBSP0 internal clock for 100 MHz operation. However, 67 MHz operation works properly. Specifically, when configured for 67 MHz operation, the CLKX signal is measured with an 0-scope to be 67 MHz. When configured for 100 MHz, the CLKX frequency measures ~ 50MHz, apparently off by a factor of 2.
I have been unable to make progress on this issue and would appreciate any advice offered
.
The relevant PLL configuration is as follows:
- CLKIN1 = 40 MHz, PREDIV=0, PLLM=29 (dec)
For a 67 MHz test, MCBSP0 is configured as follows:
- SRGR: CLKGDV = 2
- SRGR: CLKSM = 1
In this case the McBSP clock frequency is measured as ~67 MHz as predicted (40*30/6/3)
For 100 MHz operation, MCBSP0 is configured as:
- SRGR: CLKGDV = 1
- SRGR: CLKSM = 1
I would expect for this configuration to observe a CLKX frequency of (40*30/6/2)=100 MHz.
CSL is used for McBSP configuration. A relevant code segment is as follows:
CSL_McbspClkSetup mcbspClock = {
CSL_MCBSP_FSCLKMODE_INTERNAL, /* XMT Frame-sync */
CSL_MCBSP_FSCLKMODE_EXTERNAL, /* RCV Frame-sync */
CSL_MCBSP_TXRXCLKMODE_INTERNAL, /* XMT clock */
CSL_MCBSP_TXRXCLKMODE_EXTERNAL, /* RCV clock */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* XMT Frame-sync active high */
CSL_MCBSP_FSPOL_ACTIVE_HIGH, /* RCV Frame-sync active high */
CSL_MCBSP_CLKPOL_TX_FALLING_EDGE, /* XMT clock rising edge */
CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,/* RCV clock falling edge */
0, /* Frame-sync pulse width = 1 bit */
0x20, /* Frame-sync pulse period */
//0x1, /*clk divide by 2 100 MHz*/
0x2, /*clk divide by 3 67 MHz */
CSL_MCBSP_SRGCLK_CLKCPU,
CSL_MCBSP_CLKPOL_TX_RISING_EDGE ,/* CLKS pin signal rising edge */
CSL_MCBSP_TXFSMODE_DXRCOPY,
CSL_MCBSP_CLKGSYNCMODE_OFF /* GSYNC = 0 means no clock synchronisation */
};
thanks in advance,
Paul
