I have an OMAP-L137 designed on a board where EMIFB is connected to an FPGA and EMIFA is connected to an ISSI - IS42S16160D-7B 32-MegBytes SDRAM chip.
I have EMIFB configured and working correctly however, I can't even get a clock out of the EMIFA port.
I set up the PinMux Registers:
void Setup_System_PinMUX(void) // Setup Pin Mux and other system module registers
{
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
// ------------------------------------------------------------------------------------------------------------------------------------
// ===== Set pins up for (EMIF-B 32-bit FPGA Interface), SPI[0], SPI[1], UART[1], EMIF-A 16-Bit SDRAM Interface, ISR_Done and IRQ =====
// ===== NOTE: Use PinMUX Utility to Verify =====
// ---------------------------+-----------+-----------+-----------+-----------+-----------+-------------+------------+-----------+-----
// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
// -------------------------+-----------+-----------+-----------+-----------+-----------+-------------+------------+-----------+-------
PINMUX0 = 0x11112100; // - EMB_WE, EMB_RAS, EMB_CAS, EMB_CS[0], EMB_CLK, EMB_SDCKE, GP7[15], GP7[14]
PINMUX1 = 0x11111111; // - EMB_A[5], EMB_A[4], EMB_A[3], EMB_A[2], EMB_A[1], EMB_A[0], EMB_BA[0], EMB_BA[1]
PINMUX2 = 0x11111111; // - EMB_D[31], EMB_A[12], EMB_A[11], EMB_A[10], EMB_A[9], EMB_A[8], EMB_A[7], EMB_A[6]
PINMUX3 = 0x11111111; // - EMB_D[23], EMB_D[24], EMB_D[25], EMB_D[26], EMB_D[27], EMB_D[28], EMB_D[29], EMB_D[30]
PINMUX4 = 0x11111111; // - WE_DQM3, EMB_D[16], EMB_D[17], EMB_D[18], EMB_D[19], EMB_D[20], EMB_D[21], EMB_D[22]
PINMUX5 = 0x11111111; // - EMB_D[6], EMB_D[5], EMB_D[4], EMB_D[3], EMB_D[2], EMB_D[1], EMB_D[0], WE_DQM2
PINMUX6 = 0x11111111; // - EMB_D[14], EMB_D[13], EMB_D[12], EMB_D[11], EMB_D[10], EMB_D[9], EMB_D[8], EMB_D[7]
PINMUX7 = 0x00000111; // - SPI0_SCS0, SPI0_ENA, SPI0_CLK, SPI0_SIMO, SPI0_SOMI, WE_DQM[0], WE_DQM[1], D[15]
PINMUX8 = 0x10000111; // - SPI1_ENA, Pin_T4, Pin_N3, Pin_P3, Pin_R3, SPI1_CLK, SPI1_SIMO, SPI1_SOMI
PINMUX9 = 0x00800001; // - Pin_C4, Pin_B4, GP2[14], Pin_D5, Pin_C5, Pin_B5, Pin_E4, SPI1_SCS0 ***(GP2[14] is Pin_A4 ISR_Done)***
PINMUX10 = 0x00000000; // - Pin_D7, Pin_C7, Pin_B7, Pin_A7, Pin_D8, Pin_C8, Pin_B8, Pin_L4
PINMUX11 = 0x00001108; // - Pin_K4, Pin_K3, Pin_K2, Pin_A5, UART1_TXD, UART1_RXD, Pin_B6, GP3[7] ***(GP3[7] is Pin_A6 IRQ from FPGA***
PINMUX12 = 0x00000000; // - Pin_P1, Pin_P2, Pin_R2, Pin_T3, Pin_D4, Pin_L3, Pin_L2, Pin_L1
PINMUX13 = 0x11000000; // - EMA_D[1], EMA_D[0], Pin_M1, Pin_M2, Pin_M3, Pin_M4, Pin_N1, Pin_N2
PINMUX14 = 0x11111111; // - EMA_D[9], EMA_D[8], EMA_D[7], EMA_D[6], EMA_D[5], EMA_D[4], EMA_D[3], EMA_D[2]
PINMUX15 = 0x11111111; // - EMA_A[1], EMA_A[0], EMA_D[15], EMA_D[14], EMA_D[13], EMA_D[12], EMA_D[11], EMA_D[10]
PINMUX16 = 0x11111111; // - EMA_A[9], EMA_A[8], EMA_A[7], EMA_A[6], EMA_A[5], EMA_A[4], EMA_A[3], EMA_A[2]
PINMUX17 = 0x11111111; // - EMA_CAS, EMA_SDCKE, EMA_CLK, EMA_BA[0], EMA_BA[1], EMA_A[12], EMA_A[11], EMA_A[10]
PINMUX18 = 0x11100111; // - WE_DQM[0], WE_DQM[1], EMA_OE, EMA_CS[3], EMA_CS[2], EMA_CS[0], EMA_WE, EMA_RAS
PINMUX19 = 0x00000001; // - RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, EMA_WAIT[0]
// ------------------------------------------------------------------------------------------------------------------------------------
// -- CHIP CONFIG 2 Register: Enable USB1 clock --- *** See SPRUFK4D page-188,189 ***
CFGCHIP2 = 0x0000EB42; // -- USB[1]PHYCLKMUX=1 | USB[0]PHYCLKMUX=1 | USB[1]SUSPENDM=0 | USB[0]PHYPWDN=0 | USB[0]PHY_PLLON=1 | USB[0]REF_FREQ=2 24 MHz
}
Then set up the PLL:
void Setup_PLL(void)
{
int i = 0;
// -- Configure DSP at 300MHz, EMIFA at 133MHz, EMIFB Programmable from 100, 75, 60 or 50MHz -----
// -----------------------------------------------------------------------------------------------
unsigned int CLKMODE = 0; // -- Select the Clock Mode for (Oscillator = 1) or (Crystal = 0)
unsigned int PLLM = 24; // -- 24MHz(Crystal) * (24+1)Multiplier = 600MHz
unsigned int POSTDIV = 1; // -- 600MHz / (1+1)PostDivide = 300MHz (This is the Processor Clock)
unsigned int PLLDIV3 = 2; // -- This can be used for EMIFA if 4.5 Divider is not used (300MHz / (2+1) = 100MHz)
// unsigned int PLLDIV5 = 2; // -- EMIFB clock divider 300/(2+1) = 100.00 MHz
// -- These lower frequencies have over and under-shoot that cause clock voltage swings in excess of 4.5Volts ---
unsigned int PLLDIV5 = 3; // -- EMIFB clock divider 300/(3+1) = 75.00 MHz
// unsigned int PLLDIV5 = 4; // -- EMIFB clock divider 300/(4+1) = 60.00 MHz
// unsigned int PLLDIV5 = 5; // -- EMIFB clock divider 300/(5+1) = 50.00 MHz
unsigned int PLLDIV7 = 7; // -- This is for EMAC (Not Used)
// -- {Original Line in this file} This will Set PLLEN=0 (Bypass Mode) then wait for 4-Clock Cyles ---
PLL0_PLLCTL &= 0xFFFFFFFE; for(i=0; i<4; i++) {;}
// -- This will Set PLLEN=0 (Bypass Mode) and PLLRST=0 (Reset PLL) then wait for 4-Clock Cyles (SPRUFK4D page-75) ---
// PLL0_PLLCTL &= 0xFFFFFFF6; for(i=0; i<4; i++) {;}
// -- Select the Clock Mode bit 8 (Oscillator = 1) or (Crystal = 0) ---
PLL0_PLLCTL &= 0xFFFFFEFF; // -- First set bit-8 = 0
PLL0_PLLCTL |= (CLKMODE<<8); // -- Then change it to 1 if CLKMODE = 1
// -- Clear PLLENSRC (bit-5) for PLLEN (Set to bypass mode) to have effect ---
PLL0_PLLCTL &= 0xFFFFFFDF;
// -- Not sure wat this does or what this comment means (/*EXTCLKSRC (bit-9) should be left at 0 for Primus*/)
// -- Bit-9 is reserved and should always be zero.
PLL0_PLLCTL &= 0xFFFFFDFF;
// -- Clear PLLRST (bit-3). Reset the PLL. (This will hold it in reset until bit-3 is set to 1.) ---
PLL0_PLLCTL &= 0xFFFFFFF7;
// -- Disable the PLL output. Set PLLENSRC (Bit-5) to 1 ---
PLL0_PLLCTL |= 0x00000010;
// ----------------------------------
// -- PLL initialization sequence ---
// ----------------------------------
// -- The DSP comes out of Reset with the PLL in PowerDown Mode. Clear PWRDN (bit-2) to bring the PLL out of power down mode. ---
PLL0_PLLCTL &= 0xFFFFFFFD;
/*Enable the PLL from Disable Mode PLLDIS bit to 0 - */
// -- This Clears Bit-4 (a reserved bit). I don't think this is correct so I commented it out.
// PLL0_PLLCTL &= 0xFFFFFFEF;
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
// for(i=0; i<PLL_STABILIZATION_TIME; i++) {;} // Make PLL_STABILIZATION_TIME as bootpacket
// -- Program the required multiplier value in PLLM. This brings the 24Mhz crystal up to 600MHz ---
PLL0_PLLM = PLLM;
// -- Program the POSTDIV ratio. This gives you the final DSP clock frequency ---
PLL0_POSTDIV = 0x8000 | POSTDIV;
// -- Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress ---
while(PLL0_PLLSTAT & 0x1==1){}
// -- Program the RATIO field in PLLDIVx with the desired divide factors. ---
// -- Make sure you leave the DxEN (bit-15) set so clocks are still enabled (default). ---
PLL0_PLLDIV3 = 0x8000 | PLLDIV3;
PLL0_PLLDIV5 = 0x8000 | PLLDIV5;
PLL0_PLLDIV7 = 0x8000 | PLLDIV7;
// -- Set the GOSET (bit-0) in PLLCMD to initiate a new divider transition (GO bit for SYSCLKx phase alignment). ---
PLL0_PLLCMD |= 0x1;
// -- Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment). ---
while(PLL0_PLLSTAT & 0x1==1) { }
// -- Set the PLLRST (bit-3) in PLLCTL to 1 to bring the PLL out of reset ---
PLL0_PLLCTL |= 0x8;
// -- Wait for PLL to lock. See PLL spec for PLL lock time ---
for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}
KICK0R = 0x83e70b13; // -- Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // -- Kick1 register + data (unlock)
// -- Only the first three bits(0-2) in this register are used. All other bits are reserved with default values (0x0000FF0x) -----
// -- Enable 4.5 divider PLL (Bit2=1), EMIFA->SYSCLK3 (Bit1=0), EMIFB->SYSCLK5 (Bit0=0), All other bits default -----
// -- *** See SPRUFK4D page-190 ***
// -- For some reason, the DIV4.5 needs to be enabled even though it is not sourcing EMIFA or EMIFB. -----
CFGCHIP3 = 0x0000FF04; // -- 4 = 0100 (Enable DIV4.5 | EMIFA uses SYSCLK3 | EMIFB uses SYSCLK5)
// CFGCHIP3 = 0x0000FF00; // >>> 4 = 0000 (DisEnable DIV4.5 | EMIFA uses SYSCLK3 | EMIFB uses SYSCLK5) !!! Does NOT work !!!
// -- Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode ---
PLL0_PLLCTL |= 0x1;
}
Then I set the Power-Sleep Controllers to All On.
Then set up the EMIFA Registers.
void Setup_EMIFA(void)
{
int i;
EMIFA_SDTIMR = 0 // -- SDRAM Refresh Control Register (SDRCR). Bits 31-13 are reserved
|(12 << 27) // -- Bits(31-27) [T_RFC] - 10-Cycles
|( 4 << 24) // -- Bits(26-24) [T_RP] - 20ns
|( 0 << 23) // -- Bits(23) [Reserved] - default is 0
|( 4 << 20) // -- Bits(22-20) [T_RCD] - 20ns
|( 0 << 19) // -- Bits(19) [Reserved] - default is 0
|( 7 << 16) // -- Bits(18-16) [T_WR] - ??ns
|( 7 << 12) // -- Bits(15-12) [T_RAS] - 42ns
|( 9 << 8) // -- Bits(11-8) [T_RC] - 67.5ns
|( 0 << 7) // -- Bits(7) [Reserved] - default is 0
|( 5 << 4) // -- Bits(6-4) [TRRD] - 14ns
|( 0 << 0 ); // -- Bits(3-0) [Reserved] - default is 0
EMIFA_SDSRETR = 0 // -- SDRAM Self Refresh Exit Timing Register (SDSRETR). Bits 31-5 are reserved
|( 25 << 0 ); // -- Bits(4-0) Min number of Cycles from SelfRefresh-to-AnyCommand
EMIFA_SDRCR = 0 // -- SDRAM Refresh Control Register (SDRCR). Bits 31-13 are reserved
|( 3500 << 0 ); // -- Bits(12-0) Max Refresh rate for this SDRAM is 64mSec = 6400-Cycles at 100MHz (6400 => 0x1900)
EMIFA_SDCR = 0 // -- SDRAM Configuration Register (SDCR). Bits 31-13 are reserved
|( 0 << 31) // -- Bits(31) [SD] - Self Refresh Mode - 0=ExitSelfRefresh : 1=EnterSelfRefresh
|( 0 << 30) // -- Bits(30) [PD] - Power Down Bit - 0=ExitPowerDown : 1=EnterPowerDown
|( 1 << 29) // -- Bits(29) [PDWR] - Perform Refresh During PowerDown - 1=Exit PowerDown and Issue Auto-Refresh
|( 0 << 15) // -- Bits(28-15) [Reserved] - default is 0
|( 0 << 14) // -- Bits(14) [NM] - Narrow Mode - 0=32-Bit(Impossible) : 1=16-Bit
|( 0 << 12) // -- Bits(13-12) [Reserved] - default is 0
|( 3 << 9) // -- Bits(11-9) [CL] - CAS Latency - 2=2-ClockCycles : 3=3-ClockCycles
|( 1 << 8) // -- Bits(8) [BIT11_9LOCK] - 0=Locked : 1=UnLocked
|( 0 << 7) // -- Bits(7) [Reserved] - default is 0
|( 2 << 4) // -- Bits(6-4) [IBANK] - Internal SDRAM Bank Size (0=1-Bank : 1=2-Bank : 2=4-Bank)
|( 0 << 3) // -- Bits(3) [Reserved] - default is 0
|( 1 << 0 ); // -- Bits(2-0) [PAGESIZE] - Number of Columns (0=8-Col : 1=9-Col : 2=10-Col : 3=11-Col)
i = *(int*)(0x4000000); // -- Read
for(i=0; i<100; i++) ; // -- Delay
i = *(int*)(0x4000008); // -- Read
EMIFA_SDRCR = 0 // -- SDRAM Refresh Control Register (SDRCR). Bits 31-13 are reserved
|( 5000 << 0 ); // -- Bits(12-0) Max Refresh rate for this SDRAM is 64mSec = 6400-Cycles at 100MHz (6400 => 0x1900)
}
At this point I would expect to see a 100MHz clock on the EMIFA-CLK pin.
All I have are 20kHz pulses on CAS, corresponding to the 5000-ClockCycle Refresh Period that I set up in the EMIFA_SDRCR Register.
CS0 is Low and all other control lines are high, EMIFA-CLK pin is high.
What am I missing here?
