HDMI driver 8148

Sylvian,

The HDMI transmitter outputs are designed to be compliant with the HDMI standard which does not allow for series resistances etc...

Are you 100% sure that the EMI is being generated by the HDMI output? Where are your spikes? What resolution are you driving when you see these spikes?

Have you ensured that your PCB layout is fully impedance controlled, with good solid ground planes, non-overlapping signals etc...

Are you able to add series chokes to see if that helps reduce your emissions?

There are no direct registers to control the slew rate. The device is trimmed at manufacture to make the output compliant with the HDMI standard. I believe that the initial engineering samples sent out did not include the trimming, so depending on how old the particular device is that you are looking at it may not have been trimmed.

BR,

Steve

Hi Steve

The spectrum analyser show pulses synchronized with the blanking period of HDMI configured at 1080P.

We use ground plane under the hdmi pair with controlled impedance. We have 2 via on each line. We use common mode filter choke on each pair.

Here is what is written on the chip we use.

X8148X3874BCYE

1CZFWQ9

662 CYE

Can you tell what is the adress of this register TMDS_CNTL2 (HDMI_PHY Register)

I only see the offset is 04h but i am not able to determine the full 32 bit address to do a test to activate bit 4.  Termination enable.

Thanks

Sylvain

What frequency is the EMI? Is it a fundamental of the pixel rate or of the line rate?

I would be surprised if it is a fundamental of the line frequency since the HDMI protocol at the physical layer is designed to try and spread fundamental frequency noise by doing 8b-10b coding. Having said this transitions are maximized during blanking, so there is certainly a difference in emissions between active video and blanking.

Do you get the same issue when you unplug the HDMI cable (i.e. does this appear to be a device emission or a trace/cable emission)?

The base address of the phy is 0x46c00300

BR,

Steve

i have done the following commands base on the adress you provided.

colorbar

base 0x46c00000

md.l 0x304 1

46c00304: f000 0000

mw.l 0x304 0x0

And the color bar was still running.

The spec show that TMDS_CNTL2 bit <5> OE should turn off the output driver of TMDS output.

Are we at the right adress?

Hi,

Following is procedure to put PHY in power off mode.

1. Write 0x0 to bits 6:7 at register 0x46c00040u

2. Read bits 4:5 at register 0x46c00040u

Once these bits reads 0 phy should be turned off.

Regards,

Hardik Shah

Hi,

Make sure that you accidentally dont modify other bits in register. So please read register first, set bit accordingly and than write.

Regards,

Hardik Shah

Do you have any doc on this register 0x46c00040? We can not find it in the technical reference manual rev. February 2012.

Is this the HDMI_WP Register group offset 0x40?

Also can you provide a bit description of this register 0x46c00304?

Thanks

Hi,

Yes 0x46c00040 is a register from HDMI_WP group. It will be very difficult to share register level details here. Please contact your local FAE for getting register details. This may require some kind of NDA in place.

Regards,

Hardik Shah