c6678 timer interrupts

/**  
 * @file multicore_example.c
 *
 * @brief 
 *  Example to illustrate the usage of EMAC CPSW3G switch using CPPI, QMSS
 * 	low level drivers and CSL.
 *
 * 	This example application does the following:
 * 	    (1) Initializes:
 * 	            (a) Queue Manager (QM) Subsystem 
 * 	            (b) Packet Accelerator (PA) CPPI DMA 
 * 	            (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO)
 * 	            (d) PA Subsystem + PDSP
 *
 * 	    (2) Sets up the CPPI descriptors and Queues required for sending and
 * 	        receiving data using Ethernet.
 * 	            (a) Uses Host descriptors
 * 	            (b) Uses High Priority Accumulation interrupts
 *
 * 	    (3) Sets up the example application's configuration (MAC address
 * 	        it uses to send/recv data; IP address and port number it's listening
 * 	        on) in PA Subsystem so as to enable the PASS to forward all packets
 * 	        matching this configuration onto the application for processing.
 * 	            (a) Switch MAC address configured   =   0x10:0x11:0x12:0x13:0x14:0x15
 * 	            (b) Example's IP address            =   192.168.1.10
 * 	            (c) Example App's listening port    =   0x5678
 *
 * 	    (4) Sends packets onto wire 
 * 	        (constructed manually in code here with following settings):
 * 	            (a) Source MAC      =   0x00:0x01:0x02:0x03:0x04:0x05
 * 	                Destination MAC =   0x10:0x11:0x12:0x13:0x14:0x15
 *              (b) Source IP       =   192.168.1.1
 *                  Destination IP  =   192.168.1.10
 *              (c) Source Port     =   0x1234
 *                  Destination Port=   0x5678
 *              (d) Payload Data (80 bytes)
 *
 *          The packets sent by the application are sent onto wire and 
 *          since the destination MAC on the packet is the Ethernet Switch 
 *          MAC address, the packets are received by simulator and passed 
 *          back up to the example application for processing.
 *      
 *      (5) Application receives all packets using QM High priority interrupt
 *          registered; Validates received packet against data sent.
 *
 *  Example application Setup:
 *
 *          PC Running Simulator using CCS connected to a
 *          Switch/Hub. You could put another PC on the Hub to observe packets 
 *          being sent onto wire. 
 *
 *          Please consult the Readme.txt packaged with the example to 
 *          setup the CCS simulator configuration required to run this example 
 *          succesfully.
 *
 *  \par
 *  ============================================================================
 *  @n   (C) Copyright 2009, Texas Instruments, Inc.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#include <multicore_example.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_psc.h>
#include <ti/csl/csl_pscAux.h>
#include <ti/csl/csl_tmr.h>
#include <ti/csl/csl_tmrAux.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/src/intc/csl_intcAux.h>

/* PA LLD include */
#include <ti/drv/pa/pa.h>


/**************************************************************
************************** DEFINITIONS ************************
***************************************************************/
/* Number of packets to be used for testing the example. */
#define                     MAX_NUM_PACKETS                         10u


/**************************************************************
************************* GLOBAL VARIABLES ********************
***************************************************************/
/* Counters to track number of packets sent/received by this application */
extern volatile UInt32		 gRxCounter, gTxCounter, gSavedRxCounter;

/*
 * Default test configuration for the silicon
 *
 * To run test at the CCS simulator
 *    cpswSimTest = 1
 *    cpswLpbkMode = CPSW_LOOPBACK_EXTERNAL
 */
#ifdef  SIMULATOR_SUPPORT
Int cpswSimTest = 1;
Int cpswLpbkMode = CPSW_LOOPBACK_EXTERNAL;
#else
Int cpswSimTest = 0;
//Int cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;
Int cpswLpbkMode = CPSW_LOOPBACK_NONE;
#endif
Int cpswEvm6678 = 1;

/* multicore sync up variables */
#pragma DATA_ALIGN   (globalCfgDone, 128)
#pragma DATA_SECTION(globalCfgDone,   ".sharedDDR")
volatile UInt32  globalCfgDone = FALSE;   

#pragma DATA_ALIGN   (localCfgDone, 128)
#pragma DATA_SECTION(localCfgDone,    ".sharedDDR")
/* number of local configuration completed */
volatile UInt32  localCfgDone = 0;        

#pragma DATA_ALIGN   (readyToSendPkts, 128)
#pragma DATA_SECTION(readyToSendPkts, ".sharedDDR")
volatile UInt32  readyToSendPkts = FALSE;      

/**************************************************************
**************** EXAMPLE APP FUNCTIONS ************************
***************************************************************/

/* INTC Objects */
CSL_IntcObj                  tmrIntcObj;
CSL_IntcContext              context;
CSL_IntcEventHandlerRecord   EventHandler[30];

/* Global Variable for the INTC Module; useful for debugging. */
CSL_IntcRegsOvly    gIntcRegisters    = (CSL_IntcRegsOvly)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;

/* Counter for Timer ISR */
volatile Int32 timerISRCounter = 0;

/**
 *  @b Description
 *  @n
 *      This is the Timer ISR handler which is invoked when the timer expires
 *
 *  @param[in]  arg
 *      Event ID which caused the ISR to be invoked.
 *
 *  @retval
 *      Not Applicable.
 */
static void TimerTick (void *arg)
{
    /* Increment the number of interrupts detected. */
    timerISRCounter++;

    /* Clear the event ID. */
    CSL_intcEventClear((CSL_IntcEventId)arg);
}

/**
 *  @b Description
 *  @n
 *      This function is used to setup the HI Timer in Continuous Mode
 *
 *  @param[in]  IntcInstance
 *      Timer Instance Number
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static Int32 setup_high_continuous_timer (Uint8 IntcInstance)
{
    CSL_TmrHandle               hTmr;
    CSL_TmrObj                  TmrObj;
    CSL_Status                  status;
    CSL_TmrHwSetup              hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
    CSL_IntcEventHandlerRecord  EventRecord;
    CSL_IntcParam               vectId;
    CSL_IntcHandle              tmrIntcHandle;
    Uint32                      LoadValue = 1666667;
    Uint32                      LoadCntValue = 0;
    CSL_TmrEnamode              TimeCountMode = CSL_TMR_ENAMODE_CONT;
    Uint32                      count;
	int i;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    System_printf("Debug: Setup High Timer (Unchained) in Continuous Mode....\n");

    /**************************************************************
     ********************** INTC related code *********************
     **************************************************************/

    /* Open INTC */
    vectId = CSL_INTC_VECTID_13;
    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_GEM_TINTHN, &vectId, NULL);
    if (tmrIntcHandle == NULL)
        return -1;

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerTick;
    EventRecord.arg     = (void *)CSL_GEM_TINTLN;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************
     ********************** Timer related code ********************
     **************************************************************/

    /* Open the timer. */
    hTmr =  CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
    if (hTmr == NULL)
        return -1;

    /* Open the timer with the defaults. */
    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Stop the Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);

    /* Set the timer mode to unchained dual mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;
    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Reset the timer ISR Counter. */
    //timerISRCounter = 0;

    /* Load the period register */
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDHI, (void *)&LoadValue);

    /* Load the initial count register */
    //status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PSCHI, (void *)&LoadCntValue);

	System_printf("TSCL=%d timerCntr=%d\n",TSCL,timerISRCounter);
    /* Start the timer in CONTINUOUS Mode. */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMHI, (void *)&TimeCountMode);

	while (1)
	{
		// Block here until receiving a semaphore signal to signal a 10ms cycle time
		CycleDelay(10000000);
		System_printf("TSCL=%d timerCntr=%d\n",TSCL,timerISRCounter);
	}

    /* Wait for the timer interrupts to fire...*/
    while (timerISRCounter <= 0);
	System_printf("TSCL=%d timerCntr=%d\n",TSCL,timerISRCounter);
    timerISRCounter = 0;

    /* Since the HIGH Counter is operating in Continuous Mode; the value here should
     * be non-zero. Though there is a small probability that the value here could be 0. */
    //CSL_tmrGetTimHiCount(hTmr, &count);
    //if (count == 0)
    //{
        /* Taking into account the small probability; lets confirm out again.
         * This time for sure the value should be non-zero. */
    //    CSL_tmrGetTimHiCount(hTmr, &count);
    //    if (count == 0)
    //        return -1;
    //}

    /**************************************************************/

    /* Disable the events. */
    //CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

    /* Stop the Timer */
    //CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);

    /* Close the Tmr and Interrupt handles. */
    //CSL_tmrClose(hTmr);
    //CSL_intcClose(tmrIntcHandle);

	while(1)
	{
		// Block here until receiving a semaphore signal to signal a 10ms cycle time
		System_printf("TSCL=%d timerCntr=%d\n",TSCL,timerISRCounter);
		//CycleDelay(5000000);
	}

    /* Test has completed successfully. */
    return 0;
}

/***************************************************************************************
 * FUNCTION PURPOSE: Power up PA subsystem
 ***************************************************************************************
 * DESCRIPTION: this function powers up the PA subsystem domains
 ***************************************************************************************/
void passPowerUp (void)
{

    /* PASS power domain is turned OFF by default. It needs to be turned on before doing any 
     * PASS device register access. This not required for the simulator. */

    /* Set PASS Power domain to ON */        
    CSL_PSC_enablePowerDomain (CSL_PSC_PD_PASS);

    /* Enable the clocks for PASS modules */
    CSL_PSC_setModuleNextState (CSL_PSC_LPSC_PKTPROC, PSC_MODSTATE_ENABLE);
    CSL_PSC_setModuleNextState (CSL_PSC_LPSC_CPGMAC,  PSC_MODSTATE_ENABLE);
    CSL_PSC_setModuleNextState (CSL_PSC_LPSC_Crypto,  PSC_MODSTATE_ENABLE);

    /* Start the state transition */
    CSL_PSC_startStateTransition (CSL_PSC_PD_PASS);

    /* Wait until the state transition process is completed. */
    while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_PASS));
}

/**
 *  @b Description
 *  @n
 *      The functions initializes the INTC module.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static Int32 intc_init (void)
{
    CSL_IntcGlobalEnableState   state;

    /* INTC module initialization */
    context.eventhandlerRecord = EventHandler;
    context.numEvtEntries      = 100;
    if (CSL_intcInit(&context) != CSL_SOK)
        return -1;

    /* Enable NMIs */
    if (CSL_intcGlobalNmiEnable() != CSL_SOK)
        return -1;

    /* Enable global interrupts */
    if (CSL_intcGlobalEnable(&state) != CSL_SOK)
        return -1;

    /* INTC has been initialized successfully. */
    return 0;
}

/** ============================================================================
 *   @n@b MultiCoreApp
 *
 *   @b Description
 *   @n Example application that sets up the application, sends, receives
 *      data.
 *
 *   @param[in]  
 *   @n None
 * 
 *   @return
 *   @n None
 *
 * =============================================================================
 */
Void MultiCoreApp (Void)
{
	Int32	   i;
  	UInt32     coreNum;
	Int32	   rxStatus=0;

    /* Get the core number. */
    coreNum = CSL_chipReadReg(CSL_CHIP_DNUM); 


    System_printf ("************************************************\n");
    System_printf ("*** MS Started on Core %d ***\n",coreNum);
    System_printf ("************************************************\n");

    /* Init internal cycle counter */
    TSCL = 1; 
    
    /* Disable L1 and L2 Cache */
    //CACHE_wbAllL1d (CACHE_WAIT);
    //CACHE_setL1DSize(CACHE_L1_0KCACHE);
    //CACHE_setL1PSize(CACHE_L1_0KCACHE);
    #ifndef L2_CACHE
    CACHE_setL2Size(CACHE_0KCACHE);
    #endif
    
    /* All other cores wait for core 0 to finish the global config
       and setup the QMSS/CPPI/PASS */
    if(coreNum)
    {
        System_printf ("Waiting for global config...\n");
        while(!globalCfgDone)
            SYS_CACHE_INV ((void *) &globalCfgDone, 128, CACHE_WAIT);
    }
    
    /* Core 0 does the global initialization */
    if(!coreNum)
    {
        /* Enable PASS power domain */
        passPowerUp();        
        
        /* Initialize the components required to run the example:
         *  (1) QMSS
         *  (2) CPPI
         *  (3) Ethernet switch subsystem + MDIO + SGMII
         */
        /* Initialize QMSS */
        if (Init_Qmss () != 0)
        {
            System_printf ("QMSS Global init failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("QMSS successfully initialized \n");            
        }

        /* Initialize CPPI */
        if (Init_Cppi () != 0)
        {
            System_printf ("CPPI init failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("CPPI successfully initialized \n");            
        }

        /* Init PA LLD */
        if (Init_PASS () != 0)
        {
            System_printf ("PASS init failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("PASS successfully initialized \n");            
        }

        /* Initialize the CPSW switch */
        if (Init_Cpsw () != 0)
        {
            System_printf ("Ethernet subsystem init failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("Ethernet subsystem successfully initialized \n");            
        }

        /* Setup Tx */
        if (Setup_Tx () != 0)
        {
            System_printf ("Tx setup failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("Tx setup successfully done \n");            
        }
    }
    else
    {
        SYS_CACHE_INV ((void *) &gGlobalFreeQHnd, 128, CACHE_WAIT);
        /* Cores other than 0 do local QMSS initialization */
        if (Init_Qmss_Local () != 0)
        {
            System_printf ("QMSS Local init failed \n");
            BIOS_exit (-1);
        }
        else
        {
            System_printf ("QMSS Local successfully initialized \n");            
        }
        
        /* 
         * read the actual value from memory which have been initialized by core 0
         */
        //SYS_CACHE_INV ((void *) &gRxFreeQHnd, 128, CACHE_WAIT);
        SYS_CACHE_INV ((void *) &gTxFreeQHnd, 128, CACHE_WAIT);
        SYS_CACHE_INV ((void *) gPaTxQHnd, 128, CACHE_WAIT);
        SYS_CACHE_INV ((void *) gPaL3Handles, 128, CACHE_WAIT);
        SYS_CACHE_INV ((void *) &gPAInstHnd, 128, CACHE_WAIT);
    }    

    /* Setup Rx */
    if (Setup_Rx () != 0)
    {
        System_printf ("Rx setup failed \n");
        BIOS_exit (-1);
    }
    else
    {
        System_printf ("Rx setup successfully done \n");            
    }

    /* Setup PA */
    if (Setup_PASS () != 0)
    {
        System_printf ("PASS setup failed \n");
        BIOS_exit (-1);
        
    }
    else
    {
        System_printf ("PASS setup successfully done \n");            
    }

    /* Core 0 finished the global config. Set flag so other
       cores can start their local config. */
    if (!coreNum)
    {
      globalCfgDone=TRUE;
      SYS_CACHE_WB ((void *) &globalCfgDone, 128, CACHE_WAIT);

    }  
    
    /* All cores update the counter informing that they finished their setup */
    /* The global variable is a shared resource which is being accessed from multiple cores. 
     * So here we need to protect it and ensure that there is only 1 core which is accessing 
     * it at a time. We use a Hardware Semaphore to protect this. */
    while ((CSL_semAcquireDirect (PA_APP_HW_SEM_SYS)) == 0);

    /* Invalidate the cache and make sure you get the latest from the memory. */
    SYS_CACHE_INV ((void *) &localCfgDone, 128, CACHE_WAIT);

    /* The core has completed local initialization */
    localCfgDone++;

    /* The SRIO Socket has been created. Writeback the contents to the cache. */
    SYS_CACHE_WB ((void *) &localCfgDone, 128, CACHE_WAIT);

    /* Release the hardware semaphore. */
    CSL_semReleaseSemaphore (PA_APP_HW_SEM_SYS);
    
    /* All cores wait here to sync up and send packets to PA
       at the same time. */
    System_printf ("Waiting for all cores to reach the barrier before transmission starts ... \n");
    
    while (localCfgDone != NUM_CORES)
        SYS_CACHE_INV ((void *) &localCfgDone, 128, CACHE_WAIT);
    
    /*if (!coreNum)
	{
	    if (!cpswSimTest)
	    {
	        System_printf("Following is the ALE table before transmits or receives.\n");
	        view_ale_table();	// Added by Atsushi
	    }
	}*/

    System_printf("core %d can start receiving and sending\n", coreNum);

    /* Initialize the INTC Module. */
    if (intc_init() < 0)
    {
        System_printf ("Error: Initialization of the INTC module failed\n");
        return;
    }

    /* Initialize timer CSL module */
    CSL_tmrInit(NULL);

    /* Setup the High Timer in Continuous Mode. */
    if (setup_high_continuous_timer(CSL_TMR_0) < 0)
    {
        System_printf("Error: Setup High Timer (Unchained) in Continuous Mode FAILED\n");
        return;
    }
    //System_printf("Debug: Setup High Timer (Unchained) in Continuous Mode Passed\n");

    // Main task infinite loop
	while(1)
	{
		// Block here until receiving a semaphore signal to signal a 10ms cycle time
		System_printf("TSCL=%d timerCntr=%d\n",TSCL,timerISRCounter);
		//CycleDelay(5000000);

	    // Read, retrieve and parse incoming packet one by one until no data to read
	    while (1)
	    {
	        if(ReceivePacket() != 0)
	            rxStatus=-1;
	        while (gSavedRxCounter != gRxCounter)
	        {
	        	gSavedRxCounter = gRxCounter;
	        	System_printf("core %d Received %d packets so far... %d\n", coreNum, gRxCounter, gSavedRxCounter);
				CycleDelay (10000);
				/*if (!cpswSimTest)
				{
					if (++ ct_show_ale >= 10) {
						view_ale_table();
						ct_show_ale = 0;
					}
				}*/
	        }

			// If no more data to read 
			if (rxStatus == -1)
			{
				break;
			}
	    }
    }

    System_printf ("**********************************************\n");
    System_printf ("*** MS Ended on Core %d ***\n",coreNum);
    System_printf ("**********************************************\n");

    /* Example application done. Return success */
    BIOS_exit (0);
}

/** ============================================================================
 *   @n@b main
 *
 *   @b Description
 *   @n Entry point for single core example application.
 *
 *   @param[in]  
 *   @n None
 * 
 *   @return
 *   @n None
 * =============================================================================
 */
Int32 main (Void)
{
    Task_Params                	cpswTaskParams;
    
    /* Initialize the task params */
    Task_Params_init(&cpswTaskParams);

    /* Create the CPSW single core example task */
    Task_create((Task_FuncPtr)&MultiCoreApp, &cpswTaskParams, NULL);

    /* Start the BIOS Task scheduler */
	BIOS_start ();

	return 0;	
}