DM8168 DDR3 register initialization

Dear all,

we design a board use DM8168.

As http://processors.wiki.ti.com/index.php/Netra_DDR3_register_initialization_tools we calculating DM8168 register values,and update these register values to gel file.

Then,on http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init we use these gel file,but on DDR3_400MHZ and DDR3_531MHZ  seems something wrong.as follows,

[CortexA8] Enter 0 for EMIF0 & 1 for EMIF1

0

[CortexA8] DDR AADR=80000000

 [CortexA8]

[CortexA8] Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window

120

 [CortexA8]

 [CortexA8] Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window

40

 [CortexA8]

[CortexA8] Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window

 80

[CortexA8] DLL Lock Values at Start  d0,  d4,  d5,  d6

 [CortexA8]

 [CortexA8] ===== Seaching RD DQS GATE =====

 [CortexA8]

 [CortexA8] RD DQS GATE RATIO MAXIMUM VALUE DIDN'T CONVERGE

 [CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE

 [CortexA8]

 [CortexA8] ===== Seaching RD DQS =====

 [CortexA8]

[CortexA8] RD DQS RATIO MAXIMUM VALUE DIDN'T CONVERGE

 [CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE

 [CortexA8]

 [CortexA8] ===== Seaching WR DQS =====

[CortexA8]

[CortexA8] WR DQS RATIO MAXIMUM VALUE DIDN'T CONVERGE

 [CortexA8] WR DQS RATIO MINIMUM VALUE DIDN'T CONVERGE

 [CortexA8]

 [CortexA8] ===== END OF TEST =====

Please tell me why ?

Thanks