Exclude memory section from project

Weber,
can you check the MAP file and find out which section is being written into that space? Once you know the section name it will be easier to find out how is that section allocated, and how to exclude it.

Sasha, By inspecting the map file is how I saw that one core was writing on a memory space that shouldn't. It's a custom DDR3 subspace that I've defined by creating my own platform inside CCS. Once my 8 cores use the same platform definition, my question is how can I 'hide' some memory sections from other cores without defining platforms for each core. Weber

Weber,

Do you know what code is writing stuff into that space?  You should be able to setup a hardware probe point (I think that's what they are called) that catches a write the memory.

If you remove something from your memory map then you cannot place stuff into that memory.  If you aren't placing things into a memory segment, then go ahead and remove it from your platform.

Judah

How does your custom platform divide DDR3? Do you adjust the size of DDR3 depending on the core? For example, if you are building for Core 1, do you adjust the base address and the size of DD3 to occupy the addresses from 0x90000000 to 0x9FFFFFFF? And then in the memory map you see a section allocated to the address 0x80000000, as in
.const: 0x80000000

Is that what happens, or the problem is something else?

Hi,

There's a .map for core_2:

L2SRAM 00800000 00078000 00001a16 000765ea RW X
MSMCSRAM_MASTER 0c000000 00100000 00000000 00100000 RW X
MSMCSRAM_SLAVE 0c100000 00300000 00200000 00100000 RW X
DDR3_SLAVE_0 80000000 02000000 00600000 01a00000 RW X
DDR3_SLAVE_1 82000000 02000000 003a6aca 01c59536 RW X
DDR3_SLAVE_2 84000000 02000000 00000000 02000000 RW X
DDR3_SLAVE_3 86000000 02000000 00000000 02000000 RW X
DDR3_SLAVE_4 88000000 02000000 00000000 02000000 RW X
DDR3_SLAVE_5 8a000000 02000000 00000000 02000000 RW X
DDR3_SLAVE_6 8c000000 02000000 00000000 02000000 RW X
DDR3_MASTER 96000000 0a000000 00000000 0a000000 RW X

Core2 is using 600000 bytes from DDR3_slave0. However it shouldn't happen because my linker for core2 is:

SECTIONS
{
.text: load >> DDR3_SLAVE_1
.ti.decompress: load > L2SRAM
.stack: load > L2SRAM
GROUP: load > L2SRAM
{
.bss:
.neardata:
.rodata:
}
.cinit: load > DDR3_SLAVE_1
.pinit: load >> L2SRAM
.init_array: load > L2SRAM
.const: load >> DDR3_SLAVE_1
.data: load >> DDR3_SLAVE_1
.fardata: load >>DDR3_SLAVE_1
.switch: load >> DDR3_SLAVE_1 align = 0x8
.sysmem: load > L2SRAM
.far: load >> DDR3_SLAVE_1
.args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x0; }
.cio: load >> L2SRAM align = 0x8
.ti.handler_table: load > L2SRAM
.vecs: load >>DDR3_SLAVE_1 align = 0x400
systemHeap: load >> DDR3_SLAVE_1
.code: load >> DDR3_SLAVE_1
.defaultStackSection: load >> L2SRAM
.plt: load >> L2SRAM
xdc.meta: load >> MSMCSRAM_SLAVE, type = COPY
.heapslave: load >> DDR3_SLAVE_1

}

I didn't pointed anything into DDR3_SLAVE_0 at this core project.

How can I fix this?