Accumulator in QMSS

RCReddy

Hi All,

I went through userguide of Ti Keystone multicore navigator and frankly i didnt understand few parameter of usage accumulator. In the Following data structure

1. [max 32 queues per channel]

2. [we have 32 Hi priority channels and 16 low priority channels], so scanning can be possible for 32*48 = 1536 queues [Though there are total of 8192 queues], is this right?

3. [we have timer field, which we set for checking the threshold crossing]. say if the accumulate count didn't cross the threshold within CERTAIN TIME [this certain time is set by the timer], interrupt is raised? please confirm my understanding of accumulator as a whole.

Things i didn't understand is

1. what is the purpose of this ping/pong buffer. please explain?

2. This uint16_t queMgrIndex; is confusing.

does it stand for queue manager [0,1] ?

it is the queue index [say general purpose queues any number within 896 to 8191] ?

please explain more on this on how to fill in this value?

3. say i have 32 host descriptors to monitor/observe, what should be the value of uint16_t maxPageEntries;

and how it is related to size of ping/pong buffer. please explain clearly.

4. what is the basis to select this field listEntrySize? There are 3 options..which one to select in which situation.

typedef struct
{
/** Accumulator channel affected (0-47) */
uint8_t channel;
/** Accumulator channel command - Qmss_AccCmd_ENABLE_CHANNEL : Enable channel
* Qmss_AccCmd_DISABLE_CHANNEL : Disable channel */
Qmss_AccCmdType command;
/** This field specifies which queues are to be included in the queue group.
* Bit 0 corresponds to the base queue index, and bit 31 corresponds to the base
* queue index plus 31. For any bit set in this mask, the corresponding queue index
* is included in the monitoring function.
*
* This field is ignored in single-queue mode.*/
uint32_t queueEnMask;
/** Physical pointer to list ping/pong buffer. NULL when channel disabled */
uint32_t listAddress;
/** Queue Manager and Queue Number index to monitor. This serves as a base queue index when the
* channel in multi-queue mode, and must be a multiple of 32 when multi-queue mode is enabled. */
uint16_t queMgrIndex;
/** Max entries per list buffer page */
uint16_t maxPageEntries;
/** Number of timer ticks to delay interrupt */
uint16_t timerLoadCount;
/** Interrupt pacing mode. Specifies when the interrupt should be trigerred */
Qmss_AccPacingMode interruptPacingMode;
/** List entry size. Specifies the size of each data entry */
Qmss_AccEntrySize listEntrySize;
/** List count Mode. The number of entries in the list */
Qmss_AccCountMode listCountMode;
/** Queue mode. Moitor single or multiple queues */
Qmss_AccQueueMode multiQueueMode;
} Qmss_AccCmdCfg;

Before anyone replying,

let me be clear, i even went through examples and i couldn't understand. please explain me understanding "happenings/idea" in the accumulator.

Thanks

RC Reddy

over 14 years ago

0 ran35366 over 14 years ago

TI__Genius 12805 points

I try to explain some of the issues. If something is not clear get back to me.

1. There are 32 high priority channels, each one is associated with one queue, and each one is scan every QMSS tick. There are 16 low priority channels, each one has 32 queues (these are 16*32=512 low priority queues) and each tick one channel is scanned. Thus the maximum delay of the low priority queue is 16 ticks, while the high priority queues is 1 tick. 32+16=48 channels.
2. Now the mask value is clear (this is for the low priority channels, which queues are enabled and which are not). The same is true for queue manager index.
3. The QMSS has the ability to move descriptors from high priority queue into the local memory of each core. And as with any efficient data move, there is a way to have ping-pong buffer structure so that when the core is busy working on the previous descriptor, the next one is loaded into its local memory. To understand better the ping-pong concept, read the code with the comments on page 6.6 of the Navigator User’s Guide (SPRUGR9D September 2011 )

Ran

0 RCReddy over 14 years ago in reply to ran35366

Genius 3575 points

Hi Ran,

1. your first point (w.r.t to high priority channels) contradicts with Ti document.

" The 48-channel version provides channels 0 to 31 that are high, and channels 32 to 47 that are low — serviced one at a time through each iteration through channels 0 to 31. Note that any channel in any version of the firmware may be configured to monitor 32 contiguous queues, not just the low priority channels ".

with above statement, i understand that with any channel, i can monitor 32 queues.

From your statement, "each tick one channel is scanned", so i can assume that all 32 queues will be scanned in "one Tick Time".

2. I didn't understand this point clearly, please explain in detail.

3. I did read that document and understand that if there are N=16 packets to be transmitted/received, on the receive side

the size of the (16/2)+1 = 9

PAGE 0

Array[0]....................Array[8]

Array[0] contains the count of number of valid entries [between Array[1] ....Array[8] ]

Array[1] ....Array[8] contains Received descriptor ADDRESSES

PAGE 1

Array[9]....................Array[17]

Array[9] contains the count of number of valid entries [between Array[10]................Array[17] ].

Array[10]................Array[17] contains Received descriptor ADDRESSES

ListEntrySize stands at 9.

please confirm/correct my understanding.

Thanks

RC Reddy

0 ran35366 over 14 years ago in reply to RCReddy

TI__Genius 12805 points

I belive that all channels can be configured to monitor 32 queues if you change the firmware. The current firmware that is loaded into the PDSP does not support all channels. As far as I know, TI discourages users from modifying teh firmware.

About the other issues. I want to look further into it, and if necessary I will submit a request to add to the documentation

Ran

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Accumulator in QMSS