Hi,
We are configuring AM3359 McSPI port 1 to work in the slave mode with receive-only, 8-bit WL. The POL and PHA in the channel(0) Configuration registers are set to 0x3.
The physical input SPI signal is 0x84 as measured by the oscilloscope, however when read the data fromt he McSPI Rx data register, the value is 0x42.
In the TRM Rev.E, page 4130, there is some description about shifting received data bit into the shift register. "Each data frame is transmitted starting with the MSB. At the extremity of both SPI data lines, the first bit of SPI word is valid on the next SPICLK edge, a half-cycle later of SPICLK. It is the sampling edge for both the master and slave.
When the third edge occurs, the received data bit is shifted into the shift register. The next data bit of the master is provided to the serial input pin of the slave."
This description looks require one additional clock edge to shift all the received data (e.g.8 bits) into the shift register. If this is true, it can explain why we get 0x42 for a 0x84 input, but for 8-clock input ( one 8-bit transmission), it is not reasonable to add extra half clock to clock into the received data into the shift register.
Perhaps need other setting of SPI to resolve this. But don't know how?