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C667x CVDD min/max versus CoreClock frequency

markus desgronte
Prodigy 150 points

I have a question concerning the CVDD voltage. As I understand it at the moment the CVDD voltage varies from 0.9V to 1.1V from chip to chip, each chip will be programmed with the min. CVDD voltage during manufacturing. This min voltage could be different from chip to chip. The C667x than sends these information during startup via its VID-interface to the voltage controller.

My question now is what happens when I use a 1.25GHz C667x but run it only at 1.0GHz, is than the CVDD voltage which is send from the C667x over the VID interface to the voltage controller lower compared to running at 1.25GHz. Or asked in other words, is the inside the DSP programmed  min CVDD a function of the Corefrequency or is it always the same.

Thx,

Markus

  • 0
    TI__Mastermind 30825 points

    The programmed SR value is not a function of frequency.  A 1.25GHz version can be run at 1.0GHz w/ the same SR value, and the same SR value will be given regardless of what operating frequency it's physically ran at.

    Also, please note that the devices are programmed with SR Class 0.  It's not a min or max value.  It is programmed with the voltage level that the device is guaranteed to operate at.  Operating it outside this range is not allowed during normal operation (during initial power up, you will need a fixed voltage level defined in the HW design guidelines until the SR's VCNTL values are taken by the SR controller to set the operating voltage level.)

    Best Regards,

    Chad