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16bit Master Parallel Port on AM3359

Sandro Viti
Prodigy 60 points
Other Parts Discussed in Thread: AM3359

Hello everybody,
we are currently evaluating the AM3359 mcu to integrate it into an existing application that use a Xilinx FPGA for a printing application. We have a beaglebone available for testing.
Basically we need to transfer large amount of data (a sort of framebuffer) from the mcu that create and manage it, to the fpga that "consumes" the data using it. (transferring to printheads). The point is the speed of this transfer: we have a requisite to transfer to AT LEAST 10 Mbyte/s.
We initially thought to an spi, but reading the tech manual, we realized it can't manage that speed. Protocol is not important at this stage.
So we thought about a 16bit wide Parallel Port to be implemented using the LIDD controller on the MCU.

What is not fully clear to me is, the LIDD controller can work independently from the raster controller, that compose together the LCD interface?
Anyone has already done this before?
Any example on this subject?

Thanks for help,

Alex

  • 0
    TI__Guru 64490 points

    Sandro Viti said:

    What is not fully clear to me is, the LIDD controller can work independently from the raster controller, that compose together the LCD interface?

    Yes, it does operating independently from the Raster controller.  Please refer to the first paragraph of Section 13.1.1 of the LCD Controller Chapter 13 in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual.

    "Each controller operates independently from the other and only one of them is active at any given time."

     

    Sandro Viti said:

    Anyone has already done this before?
    Any example on this subject?

    I have not done this and do not have an example.  It seems like a reasonable approach however.  The alternative I would suggest would be to connect the FPGA to the GPMC interface (General Purpose Memory Controller).

  • 0 in reply to BrandonAzbell
    Intellectual 365 points

    GPMC interface seems to be the easy way.

    Section 7.1.1.1 of TRM talks about up to100MHz external memory clock performance when using only one device.

  • 0 in reply to Marcelo Barros
    Prodigy 60 points

    I decided to try implementing the port using the PRUSS, or at least evaluate the idea.

    It seems to be much more complicated, but more versatile in having asynchronous behaviour in respect to the A8 core.

    Plus, the advantage to have shared memory access anyway and dedicated interrupts.., well i think it's worth a try..

    The GPIOs toggling rate seems to be much more faster than any other peripheral (5ns resolution), so this way i can achieve 10MBytes/sec transfer rate or more.

    This is what i plan, however..

  • 0
    Prodigy 60 points

    Talking about PRUSS,

    i noticed that the Rev. E (current) of the AM335X Technical Reference Manual completely miss the section 4 (PRUSS) details.

    It is reduced to 3 pages..

    I then switched back to Rev.C of the manual where the section is complete.

    Is there any reason for this?

    Finally, i suggest mantaining old revisions of the Tech.Ref. manuals available on the TI site,

    as this could have been saved to me one hour on the web searching for the Rev.C pdf file ;)

    Alex

  • 0 in reply to Sandro Viti
    Intellectual 365 points

    Yes, I agree, asynchronous behavior is a desired feature, for sure. I will investigate this option as well.

    Do we already have a C compiler for PRUSS processors ?