EDMA3 3D transfer problem

Abhishek,

My apologies for not seeing your question from last week.

With all EDMA3 operations, the triggering of a channel (DMA or QDMA) causes a single A-Sync or AB-Sync Transfer Request to be initiated. If the channel is programmed to do more than that (BCNT > 1 for A-Sync or CCNT > 1 for AB-Sync), then additional triggers are needed.

For a QDMA operation, the EDMA3 User's Guide or the EDMA3 section of the TRM has a section titled "QDMA Channels". It explains in that section that QDMA triggering events are either writes to the trigger word or the process of doing a Link operation after the transfer is completed.

In either case, there is no possibility for the valid use of CCNT > 1. For QDMA, CCNT must always be exactly 1.

The best way to do your operation is with a DMA channel (pick any unused channel) programmed the same as your QDMA channel was. But in the OPT register, use STATIC=0, TCC=<this DMA channel>, ITCCHEN=1. You did not show the rest of your OPT register, but most likely the other bits can stay the same. Be sure SAM=DAM=0.

I do not think your indexing is correct, but it might help if I understood more clearly what the dimensions / use / locations of the src and dst buffers are.

Which device are you using?

In the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review all of the modules even if this is not the device you are using. In particular, the EDMA3/QDMA/IDMA Module may help you understand some of the features and options available within the EDMA3 module. You can find the complete video set here.

Regards,
RandyP

HI Randy

Thanks for your reply. Well, through your valuable posts of the past i could able to do a ABC sync transfer through self-chaining on DM8148 EVM for DSP. For this transfer, i have set ITCCHEN = 1 and all other fields as you have mentioned in your post above.  I have noticed that for the entire chain (8 times self chained) we have to do chaining again once the CCNT decrement by 1. And in the current EDMA LLD this is not true for the EDMA channel with TCC id 0. Because zero is default setting. I hope these are right findings by me.

I have enabled TC interrupt by setting the corresponding bit. But I have a big doubt. Now the interrupt generated will be after the complete transfer of one param as per the EDMA document. Does this means that interrupt in my case for a chain for 8 elements will occur 8 times? i mean after each AB transfer on the channel takes place or it will occur only once after the final transfer on the last channel. 

I am asking this because i wann a use this for applying EDMA waits and right now even after polling for IPR bit using EDMA3_waitandClearTCC api i could not able to get the sufficient waiting over the last transfer. I could see the IPR bit getting set in my register after the transfer for the whole chain but i really doubt if it is for only once or 8 times as i mentioned before.

Hope you got my question.

Thanks a Lot

Abhishek

Abhishek,

The EDMA3 video from the video set I mentioned above adds a little to the explanation in the EDMA3 section of the TRM. This should explain where your doubt is for the interrupts.

Please provide specifics. It is not possible for me to discuss comments like "in the current EDMA LLD this is not true" or "the corresponding bit". You should be able to everything properly in the EDMA3 LLD and if you set the correct corresponding bit then you will not have doubts about the operation.

Can you test your system to determine if your doubts are correct or not?

Regards,
RandyP

Hi Randy

I am sorry if my post is difficult to clear my point. Let me make it simple.

I am doing the self-chaining and my chain is 8 elements long . For eg.

Channel 1------>Channel 1------>Channel 1------->Channel 1------>Channel 1--------->Channel 1------>Channel 1--------Channel 1

Now for this i am using the following API to chain :- EDMA3_DRV_chainChannel() .

When I self chain i set the ITCCHEN=1 and TCINTEN=1. 

So my question is since i am doing self chaining (8-elements) will my interrupt occur after each 2-D Transfer on channel 1?

This is because TCINTEN is 1 for all 8 elements since they belong to the same channel.

Had it been a non-self linking case then i guess by setting the TCINTEN=1 only for last channel i could have got only one interrupt upon final transfer. But in the current case of 8 elements i think 8 interrupts will occur after each 2D transfer.

I hope i am clear now.

Thanks

Abhishek