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Clock selection for C6678

John J Wu
Genius 3870 points

I need to generate clocks for the C6678 DSP. The Hardware design guide on page 20 recommends the following frequencies for the device:

-          SRIOSGMIICLK = 312.5 MHz

-          CORECLK = 122.88 MHz

-          PASSCLK = 122.88 MHz

-          DDRCLK = 66.667 MHz

The evaluation board uses different frequencies: 312.5 MHz, 100 MHz, 100 MHz, and 66.667 MHz, respectively.

We do not plan of using HyperLink MCM_CLK and PCIeCLK and terminate the inputs according to the recommendations in the Hardware design guide, Figure 5 on page 15.

 

What clocking set would be preferable for the 1.25 GHz device and why?

Is it OK to not use the HyperLink MCM_CLK and PCIeCLK and terminate the inputs according to the recommendations?

Thanks,

John

  • 0
    TI__Mastermind 46460 points

    John,

    The frequencies listed above from the Hardware Design Guide are reasonable recommendations for a C6670 device which will be processing baseband radio data.  They are not common frequencies for a C6678 device.  The SERDES reference clocks are specific.  The SRIOSGMIICLK and MCMCLK can be either 156.25MHz, 250MHz or 312.5MHz.  PCIECLK can be 100MHz, 156.25MHz, 250MHz or 312.5MHz.  The other clock inputs accept a range of frequencies.  The CORECLK, PASSCLK and DDRCLK can be any frequency from 40MHz to 312.5MHz.

    Since you are not using the HyperLink interface or the PCIe interface, the PCIECLK and MCMCLK inputs can be biased as defined for unused inputs.  The SRIOSGMIICLK input can be driven with any of the 3 qualified clock input rates.  Be sure that the clock input reference meets the required jitter mask.

    Assuming that you wish to operate the DDR3 at 1333MT/s, the 66.667MHz input to DDRCLK is a good choice.  CORECLK and PASSCLK (if used) can be 100MHz.  Please note that these input rates result in simple multiply and divide settings to the PLLs and provide optimal operating rates.  However, since the PLLs attached to the DDRCLK, CORECLK and PASSCLK inputs are very flexible, the input clocks for these inputs can any rate within the valid range and you will be able to get close to the desired operating rate.

    Tom