• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 423 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MessageQ(IPC) over SRIO [Chip to Chip Communication] v/s LLD SRIO [Chip to Chip Communication]

RCReddy
Genius 3575 points

Hi All,

          if I understand clearly, assuming SRIO as BASE Communication mechanism, for CHIP (c6670) to CHIP (c6670) communication following are the options

1. Minimal worry about LLD'S [ease of use]

           IPC(MessageQ) over SRIO. Majority of the configuration is done through .CFG file, only MessageQ module API's are used.

2. More worry about LLD's [steep learning curve]

a. Direct I/O based communication.

b. Type 9 based Communication.

c. Type 11 based Communication.

=============discussion/understanding===================

  • I assume point 1 ( IPC(MessageQ) over SRIO) uses point 2C (Type 11 based Communication) ? is this correct ?
  • what is the overhead of

                  MessageQ Module (over SRIO)

                   over

                  Low Level Driver based SRIO communication ? Any comparison on data throughputs ?

  • Assuming my data transfer rate is around 700Mbps, is IPC(MessageQ) over SRIO sufficient to cater to the need? 

Thanks

RC Reddy

  • 0
    TI__Expert 8055 points

    RCReddy,

    As far as I can tell, to this point, IPC does not inherently support Communication via SRIO.   I've been looking through the IPC module (version 1.24.02.27) and the associated documentation.  Please let me know if can point me to documenation that is contrary to what I am providing here, and I will try to resolve any discrepancies.

     IPC implements the MessageQ interface, but in looking at what is currently supplied with the existing IPC module, there is no inherent support for SRIO.  The only implementation provided is ti.sdo.ipc.transports.TransportShm (shared memory).  So, in order to get this functionality, you would need to create your own interface to support it.  This interface would be built on top of the SRIO LLD.  So, for the interface implementer, there would still need to be some understanding of the LLDs.  But for any users of this interface, you're correct.  The configuration of the module would just be done at the .cfg level and the user would not need to be concerned with the implementation of the transport at all.  

    The type of SRIO communication to be used would be decided by the SRIO interface implementer.  As far as data throughput, there should be no difference between directly using the LLD and using the MessageQ module.  Each lane of 6670 SRIO is capable of 1.25 GBaud, which will result in about 780 MBps of payload, so a single lane will be enough to handle your data load.  Multiple lanes could be used if additional throughput is needed.   In terms of application overhead, there will be a small amount of cycle overhead consumed by the additional layer of software used by the interface.

    Regards,
    Dan

  • 0 in reply to DanRinkes
    TI__Expert 8055 points

    RCReddy,

    A bit of a correction to my previous post.  We do ship a driver with the MCSDK for MessageQ over SRIO.  You can find it in <pdk_install_dir>\oackages\ti\transport\ipc.  Sorry for the confusion.

    There areexamples with benchmarks supplied, so you should be able to evaluate the overhead that you are concerned about with these.

    Regards,
    Dan

     

  • 0 in reply to DanRinkes
    Genius 3575 points

    Hi Dan,

                Thanks and i am aware of that example. my questions are on that example only. i went in the code and found that it uses TYPE 11 messages.

    i.e. SrioChipToChipExample uses Type 11 communication protocol for establishing connection between two chips [the other doubt, you clarified that single Srio line might be sufficient for my work].

    The other help i need, (i asked previously in this forum), is there any internal (in developing stage, or to be devloped) example which does the both chip to chip and core to core communication.

    Here are the details

    1. Ti gave core to core communication using MessageQ(Shared Memory,Qmss Monolithic Qpend example). i am happy.

    2. Ti gave Chip to Chip Communication using MessageQ(SRIO), i am happy.

    based on 1 and 2, it would be better if Ti comes up with Example establishing Chip to Chip Communication between two boards using MessageQ (using SRIO 1) and at the same time maintaining Qmss (2) based MessageQ communication between all cores within a chip.

    let me know if you can throw a pointer in it, already justin32 suggested a solution to it in one of my posts, i wanted a reference/example for the same.

    Thanks

    RC Reddy