I did a project on C5509A with ccsv3_3 2 years ago.
I that project in one function I did division of two floating point numbers; ( x=1.0 / F , F is a floating point and changes).
I ported the project to CCsv5_1. Everything seems ok other that the floating point division which takes 5 times longer than the one I used with ccsv3_3.
I looked at the assembly codes for _divd which comes from rtslib55x . The new one which came with ccsv5_5 is much longer code. You can see assembly codes.
I was wondering why is the new _divd from ccsv5_1 is much longer than that of cssv3_3?
Best regards
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
_divd from ccsv3_3 is as follows:
016128 _divd:
016128 3876 push(T3,T2)
01612A 4ef7 SP = SP - #9
01612C eb0418 dbl(*SP(#02h)) = AC1
01612F eb0008 dbl(*SP(#00h)) = AC0
016132 ed0418 AC1 = dbl(*SP(#02h))
016135 ed0008 AC0 = dbl(*SP(#00h))
016138 7a80000a_2d01 AC0 = #-32768 << #16 || AC1 = AC1 ^ AC0
01613E 2810 AC0 = AC0 & AC1
016140 eb0c08 dbl(*SP(#06h)) = AC0
016143 ed0408 AC0 = dbl(*SP(#02h))
016146 ed0038_110729 AC3 = dbl(*SP(#00h)) || AC0 = AC0 <<< #-23
01614C ec3e32 bit(AC3, *SP(#1fh)) = #0
01614F ed0418_19ff70 AC1 = dbl(*SP(#02h)) || T3 = AC0 & #255
016155 ec3e12 bit(AC1, *SP(#1fh)) = #0
016158 041712 if (T3 != #0) goto #0x01616d
01615B 7a7f800a_9e83 if (AC3 == #0) execute(D_Unit) || AC0 = #32640 << #16
016161 1a0100 AC0 = AC0 | #1
016164 7a7f800a_9e93 if (AC3 != #0) execute(D_Unit) || AC0 = #32640 << #16
01616A 06008f goto #0x0161fc
01616D ec31be7fffff XAR3 = mar(*(#07fffffh))
016173 90b2 AC2 = XAR3
016175 2821 AC1 = AC1 & AC2
016177 3c00 AC0 = #0
016179 04111d if (AC1 != #0) goto #0x016199
01617C 107729 AC1 = AC3 <<< #-23
01617F 2216 T2 = AC1
016181 040678 if (T2 == #0) goto #0x0161fc
016184 7a00ff1a AC1 = #255 << #16
016188 7a01000a AC0 = #256 << #16
01618C 7effff11 AC1 = AC1 | #65535
016190 107001 AC1 = AC1 & (AC3 <<< #1)
016193 2410 AC0 = AC0 + AC1
016195 4a32_2776 goto #0x0161cb || T2 = T2 - T3
016199 10b729 AC2 = AC3 <<< #-23
01619C 2226 T2 = AC2
01619E 04065b if (T2 == #0) goto #0x0161fc
0161A1 90b2 AC2 = XAR3
0161A3 7a00803a_2932 AC3 = #128 << #16 || AC2 = AC2 & AC3
0161A9 7a00800a_2523 AC0 = #128 << #16 || AC3 = AC3 + AC2
0161AF 2401 AC1 = AC1 + AC0
0161B1 1a0003 AC0 = AC3 | #0
0161B4 6c016613 call _frcdivd
0161B8 7a01001a_2776 AC1 = #256 << #16 || T2 = T2 - T3
0161BE 4010 AC0 = AC0 + #1
0161C0 120814 TC1 = uns(AC0 >= AC1)
0161C3 5000_9ef4 if (!TC1) execute(D_Unit) || AC0 = AC0 <<< #1
0161C7 4216_9ef4 if (!TC1) execute(D_Unit) || T2 = T2 - #1
0161CB 7b007f66 T2 = T2 + #127
0161CF 043614 if (T2 <= #0) goto #0x0161e6
0161D2 7600ff98 AR1 = #255
0161D6 126490_21 TC1 = T2 < AR1 || nop
0161DA 3c00_9ef4 if (!TC1) execute(D_Unit) || AC0 = #0
0161DE 7600ff68_9ef4 if (!TC1) execute(D_Unit) || T2 = #255
0161E4 4a04 goto #0x0161ea
0161E6 3c00 AC0 = #0
0161E8 3c06 T2 = #0
0161EA ec31be7fffff XAR3 = mar(*(#07fffffh))
0161F0 10473f AC1 = AC0 <<< #-1
0161F3 90b0 AC0 = XAR3
0161F5 2810 AC0 = AC0 & AC1
0161F7 2261 AC1 = T2
0161F9 101317 AC0 = AC0 + (AC1 << #23)
0161FC ed0c00 AC0 = AC0 + dbl(*SP(#06h))
0161FF eb0808 dbl(*SP(#04h)) = AC0
016202 ed0808 AC0 = dbl(*SP(#04h))
016205 4e09 SP = SP + #9
016207 3a76 T3,T2 = pop()
016209 4804 return
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
_divd from ccsv5_1 is as follows:
_divd:
0x015906: 3876 PSH T3,T2
0x015908: 4ef1 AADD #-15,SP
0x01590a: eb0008 MOV AC0,dbl(*SP(#00h))
0x01590d: a000 MOV *SP(#00h),AC0
0x01590f: 76800090 BFXTR #32768,AC0,AR1
0x015913: ed0008 MOV dbl(*SP(#00h)),AC0
0x015916: 100729 SFTL AC0,#-23,AC0
0x015919: 18ffa0 AND #255,AC0,AR2
0x01591c: 7c007faa SUB #127,AR2,AR2
0x015920: 22a0 MOV AR2,AC0
0x015922: eb0408 MOV AC0,dbl(*SP(#02h))
0x015925: ed0008 MOV dbl(*SP(#00h)),AC0
0x015928: eb0018_110708 MOV AC1,dbl(*SP(#00h)) || SFTL AC0,#8,AC0
0x01592e: ec3e00 BSET *SP(#1fh),AC0
0x015931: 7affff1a MOV #-1 << #16,AC1
0x015935: eb0808 MOV AC0,dbl(*SP(#04h))
0x015938: a000 MOV *SP(#00h),AC0
0x01593a: 76800060 BFXTR #32768,AC0,T2
0x01593e: ed0008 MOV dbl(*SP(#00h)),AC0
0x015941: 100729 SFTL AC0,#-23,AC0
0x015944: 18ffa0 AND #255,AC0,AR2
0x015947: 7c007faa SUB #127,AR2,AR2
0x01594b: 7eff8111 OR #65409,AC1,AC1
0x01594f: 22a0 MOV AR2,AC0
0x015951: eb0c08 MOV AC0,dbl(*SP(#06h))
0x015954: ed0008 MOV dbl(*SP(#00h)),AC0
0x015957: 100708 SFTL AC0,#8,AC0
0x01595a: ec3e00 BSET *SP(#1fh),AC0
0x01595d: eb1008 MOV AC0,dbl(*SP(#08h))
0x015960: ed0408 MOV dbl(*SP(#02h)),AC0
0x015963: 120014 CMPU AC0 == AC1, TC1
0x015966: 04642b BCC #0x015994,TC1
0x015969: 76008018 MOV #128,AC1
0x01596d: ed0408 MOV dbl(*SP(#02h)),AC0
0x015970: 120014 CMPU AC0 == AC1, TC1
0x015973: 04641e BCC #0x015994,TC1
0x015976: 7affff1a MOV #-1 << #16,AC1
0x01597a: ed0c08 MOV dbl(*SP(#06h)),AC0
0x01597d: 7eff8111 OR #65409,AC1,AC1
0x015981: 120014 CMPU AC0 == AC1, TC1
0x015984: 6764 BCC #0x015994,TC1
0x015986: 76008018 MOV #128,AC1
0x01598a: ed0c08 MOV dbl(*SP(#06h)),AC0
0x01598d: 120c14 CMPU AC0 != AC1, TC1
0x015990: 6d640140 BCC #0x015ad4,TC1
0x015994: ed0408 MOV dbl(*SP(#02h)),AC0
0x015997: 76008018_2362 MOV #128,AC1 || MOV T2,AC2
0x01599d: 120c14 CMPU AC0 != AC1, TC1
0x0159a0: 2c92 XOR AR1,AC2
0x0159a2: 6764 BCC #0x0159b2,TC1
0x0159a4: 7a80001a MOV #-32768 << #16,AC1
0x0159a8: ed0808 MOV dbl(*SP(#04h)),AC0
0x0159ab: 120c14 CMPU AC0 != AC1, TC1
0x0159ae: 6d640088 BCC #0x015a3a,TC1
0x0159b2: 76008018 MOV #128,AC1
0x0159b6: ed0c08 MOV dbl(*SP(#06h)),AC0
0x0159b9: 120c14 CMPU AC0 != AC1, TC1
0x0159bc: 66e4 BCC #0x0159cb,TC1
0x0159be: 7a80001a MOV #-32768 << #16,AC1
0x0159c2: ed1008 MOV dbl(*SP(#08h)),AC0
0x0159c5: 120c14 CMPU AC0 != AC1, TC1
0x0159c8: 04646f BCC #0x015a3a,TC1
0x0159cb: 76008018 MOV #128,AC1
0x0159cf: ed0408 MOV dbl(*SP(#02h)),AC0
0x0159d2: 120c14 CMPU AC0 != AC1, TC1
0x0159d5: 046426 BCC #0x0159fe,TC1
0x0159d8: 7a80001a MOV #-32768 << #16,AC1
0x0159dc: ed0808 MOV dbl(*SP(#04h)),AC0
0x0159df: 120c14 CMPU AC0 != AC1, TC1
0x0159e2: 046419 BCC #0x0159fe,TC1
0x0159e5: 76008018 MOV #128,AC1
0x0159e9: ed0c08 MOV dbl(*SP(#06h)),AC0
0x0159ec: 120c14 CMPU AC0 != AC1, TC1
0x0159ef: 66e4 BCC #0x0159fe,TC1
0x0159f1: 7a80001a MOV #-32768 << #16,AC1
0x0159f5: ed1008 MOV dbl(*SP(#08h)),AC0
0x0159f8: 120014 CMPU AC0 == AC1, TC1
0x0159fb: 04643c BCC #0x015a3a,TC1
0x0159fe: 7affff1a MOV #-1 << #16,AC1
0x015a02: ed0408 MOV dbl(*SP(#02h)),AC0
0x015a05: 7eff8111 OR #65409,AC1,AC1
0x015a09: 120c14 CMPU AC0 != AC1, TC1
0x015a0c: 046444 BCC #0x015a53,TC1
0x015a0f: 7a80001a MOV #-32768 << #16,AC1
0x015a13: ed0808 MOV dbl(*SP(#04h)),AC0
0x015a16: 120c14 CMPU AC0 != AC1, TC1
0x015a19: 046437 BCC #0x015a53,TC1
0x015a1c: 7affff1a MOV #-1 << #16,AC1
0x015a20: ed0c08 MOV dbl(*SP(#06h)),AC0
0x015a23: 7eff8111 OR #65409,AC1,AC1
0x015a27: 120c14 CMPU AC0 != AC1, TC1
0x015a2a: 046426 BCC #0x015a53,TC1
0x015a2d: 7a80001a MOV #-32768 << #16,AC1
0x015a31: ed1008 MOV dbl(*SP(#08h)),AC0
0x015a34: 120c14 CMPU AC0 != AC1, TC1
0x015a37: 046419 BCC #0x015a53,TC1
0x015a3a: f4007fff AND #32767,*SP(#00h)
0x015a3e: a000 MOV *SP(#00h),AC0
0x015a40: 10210f OR AC2 << #15, AC0
0x015a43: c000 MOV AC0,*SP(#00h)
0x015a45: ed0018 MOV dbl(*SP(#00h)),AC1
0x015a48: 7a7fff0a MOV #32767 << #16,AC0
0x015a4c: 7effff00 OR #65535,AC0,AC0
0x015a50: 060271 B #0x015cc4
0x015a53: 76008018 MOV #128,AC1
0x015a57: ed0408 MOV dbl(*SP(#02h)),AC0
0x015a5a: 120c14 CMPU AC0 != AC1, TC1
0x015a5d: 6764 BCC #0x015a6d,TC1
0x015a5f: 7a80001a MOV #-32768 << #16,AC1
0x015a63: ed0808 MOV dbl(*SP(#04h)),AC0
0x015a66: 120014 CMPU AC0 == AC1, TC1
0x015a69: 6d6400c2 BCC #0x015b2f,TC1
0x015a6d: 7affff1a MOV #-1 << #16,AC1
0x015a71: ed0c08 MOV dbl(*SP(#06h)),AC0
0x015a74: 7eff8111 OR #65409,AC1,AC1
0x015a78: 120c14 CMPU AC0 != AC1, TC1
0x015a7b: 6764 BCC #0x015a8b,TC1
0x015a7d: 7a80001a MOV #-32768 << #16,AC1
0x015a81: ed1008 MOV dbl(*SP(#08h)),AC0
0x015a84: 120c14 CMPU AC0 != AC1, TC1
0x015a87: 6d7400a4 BCC #0x015b2f,!TC1
0x015a8b: 7affff1a MOV #-1 << #16,AC1
0x015a8f: ed0408 MOV dbl(*SP(#02h)),AC0
0x015a92: 7eff8111 OR #65409,AC1,AC1
0x015a96: 120c14 CMPU AC0 != AC1, TC1
0x015a99: 66e4 BCC #0x015aa8,TC1
0x015a9b: 7a80001a MOV #-32768 << #16,AC1
0x015a9f: ed0808 MOV dbl(*SP(#04h)),AC0
0x015aa2: 120014 CMPU AC0 == AC1, TC1
0x015aa5: 04641a BCC #0x015ac2,TC1
0x015aa8: 76008018 MOV #128,AC1
0x015aac: ed0c08 MOV dbl(*SP(#06h)),AC0
0x015aaf: 120c14 CMPU AC0 != AC1, TC1
0x015ab2: 04641f BCC #0x015ad4,TC1
0x015ab5: 7a80001a MOV #-32768 << #16,AC1
0x015ab9: ed1008 MOV dbl(*SP(#08h)),AC0
0x015abc: 120c14 CMPU AC0 != AC1, TC1
0x015abf: 046412 BCC #0x015ad4,TC1
0x015ac2: f4007fff AND #32767,*SP(#00h)
0x015ac6: a000 MOV *SP(#00h),AC0
0x015ac8: 10210f OR AC2 << #15, AC0
0x015acb: c000 MOV AC0,*SP(#00h)
0x015acd: 7a80000a MOV #-32768 << #16,AC0
0x015ad1: 06007a B #0x015b4e
0x015ad4: 7affff1a MOV #-1 << #16,AC1
0x015ad8: ed0408 MOV dbl(*SP(#02h)),AC0
0x015adb: 7eff8111 OR #65409,AC1,AC1
0x015adf: 120c14 CMPU AC0 != AC1, TC1
0x015ae2: 2c96 XOR AR1,T2
0x015ae4: 67e4 BCC #0x015af5,TC1
0x015ae6: f4007fff AND #32767,*SP(#00h)
0x015aea: a100_2360 MOV *SP(#00h),AC1 || MOV T2,AC0
0x015aee: 10410f OR AC0 << #15, AC1
0x015af1: c100 MOV AC1,*SP(#00h)
0x015af3: 4a58 B #0x015acd
0x015af5: ed0408 MOV dbl(*SP(#02h)),AC0
0x015af8: ed0c02 SUB dbl(*SP(#06h)),AC0,AC0
0x015afb: 760080a8_2309 MOV #128,AR2 || MOV AC0,AR1
0x015b01: 1298a0_21 CMP AR1 >= AR2, TC1 || NOP
0x015b05: eb1808 MOV AC0,dbl(*SP(#0ch))
0x015b08: 65e4 BCC #0x015b15,TC1
0x015b0a: 76ff82a8 MOV #-126,AR2
0x015b0e: 12a490_21 CMP AR2 < AR1, TC1 || NOP
0x015b12: 04644d BCC #0x015b62,TC1
0x015b15: ed1008 MOV dbl(*SP(#08h)),AC0
0x015b18: ed0818 MOV dbl(*SP(#04h)),AC1
0x015b1b: 760080a8 MOV #128,AR2
0x015b1f: 121804 CMPU AC1 >= AC0, TC1
0x015b22: 4219_9ef4 XCCPART !TC1 || SUB #1,AR1
0x015b26: 1294a0_21 CMP AR1 < AR2, TC1 || NOP
0x015b2a: 2262 MOV T2,AC2
0x015b2c: 046427 BCC #0x015b56,TC1
0x015b2f: f4007fff AND #32767,*SP(#00h)
0x015b33: a000 MOV *SP(#00h),AC0
0x015b35: 10210f OR AC2 << #15, AC0
0x015b38: c000 MOV AC0,*SP(#00h)
0x015b3a: ed0018 MOV dbl(*SP(#00h)),AC1
0x015b3d: 7a7fff0a MOV #32767 << #16,AC0
0x015b41: 7effff00 OR #65535,AC0,AC0
0x015b45: 2a10 OR AC1,AC0
0x015b47: eb0008 MOV AC0,dbl(*SP(#00h))
0x015b4a: 7aff800a MOV #-128 << #16,AC0
0x015b4e: ed0018 MOV dbl(*SP(#00h)),AC1
0x015b51: 060170_2910 B #0x015cc6 || AND AC1,AC0
0x015b56: 76ff82a8 MOV #-126,AR2
0x015b5a: 1298a0_21 CMP AR1 >= AR2, TC1 || NOP
0x015b5e: 6d74ff60 BCC #0x015ac2,!TC1
0x015b62: 7a80001a MOV #-32768 << #16,AC1
0x015b66: 7a00000a MOV #0 << #16,AC0
0x015b6a: ed1050 ADD dbl(*SP(#08h)),AC1,AC1
0x015b6d: 7e63df00 OR #25567,AC0,AC0
0x015b71: 105724 SFTL AC1,#-28,AC1
0x015b74: 2410 ADD AC1,AC0
0x015b76: 900b MOV AC0,XAR3
0x015b78: df6105 MOV uns(*AR3),AC0
0x015b7b: 100517 SFTS AC0,#23,AC0
0x015b7e: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015b81: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015b84: 6390 BCC #0x015b8d,AC0 != #0
0x015b86: 7a80000a MOV #-32768 << #16,AC0
0x015b8a: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015b8d: 3c57 MOV #5,T3
0x015b8f: ed1008 MOV dbl(*SP(#08h)),AC0
0x015b92: ed1418 MOV dbl(*SP(#0ah)),AC1
0x015b95: 6c017894 CALL _frcmpyd_div
0x015b99: 1a0010 OR #0,AC0,AC1
0x015b9c: 101701 SFTL AC1,#1,AC0
0x015b9f: 3600 NOT AC0,AC0
0x015ba1: 7b000110 ADD #1,AC0,AC1
0x015ba5: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015ba8: 6c017894 CALL _frcmpyd_div
0x015bac: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015baf: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015bb2: 5000_4317 SFTL AC0,#1 || SUB #1,T3
0x015bb6: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015bb9: 0417d3 BCC #0x015b8f,T3 != #0
0x015bbc: ed0808 MOV dbl(*SP(#04h)),AC0
0x015bbf: ed1418 MOV dbl(*SP(#0ah)),AC1
0x015bc2: 6c017894 CALL _frcmpyd_div
0x015bc6: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015bc9: ed1808 MOV dbl(*SP(#0ch)),AC0
0x015bcc: eb1808 MOV AC0,dbl(*SP(#0ch))
0x015bcf: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015bd2: 7a80001a_5100 MOV #-32768 << #16,AC1 || SFTL AC0,#1
0x015bd8: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015bdb: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015bde: 120814 CMPU AC0 >= AC1, TC1
0x015be1: 046410 BCC #0x015bf4,TC1
0x015be4: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015be7: 5000 SFTL AC0,#1
0x015be9: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015bec: ed1808 MOV dbl(*SP(#0ch)),AC0
0x015bef: 4210 SUB #1,AC0
0x015bf1: eb1808 MOV AC0,dbl(*SP(#0ch))
0x015bf4: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015bf7: 7b004000 ADD #64,AC0,AC0
0x015bfb: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015bfe: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015c01: 120814 CMPU AC0 >= AC1, TC1
0x015c04: 67e4 BCC #0x015c15,TC1
0x015c06: ed1808 MOV dbl(*SP(#0ch)),AC0
0x015c09: 4010 ADD #1,AC0
0x015c0b: eb1808 MOV AC0,dbl(*SP(#0ch))
0x015c0e: 7a80000a MOV #-32768 << #16,AC0
0x015c12: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015c15: 7affff1a MOV #-1 << #16,AC1
0x015c19: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015c1c: 7eff8011 OR #65408,AC1,AC1
0x015c20: 2810 AND AC1,AC0
0x015c22: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015c25: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015c28: 188000 AND #128,AC0,AC0
0x015c2b: 04005f BCC #0x015c8d,AC0 == #0
0x015c2e: ed1008 MOV dbl(*SP(#08h)),AC0
0x015c31: ed1418 MOV dbl(*SP(#0ah)),AC1
0x015c34: 6c017894 CALL _frcmpyd_div
0x015c38: 7a80002a MOV #-32768 << #16,AC2
0x015c3c: ed1818 MOV dbl(*SP(#0ch)),AC1
0x015c3f: ed0428_130424 MOV dbl(*SP(#02h)),AC2 || CMPU AC0 < AC2, TC1
0x015c45: 5000_9ee4 XCCPART TC1 || SFTL AC0,#1
0x015c49: ed0c50 ADD dbl(*SP(#06h)),AC1,AC1
0x015c4c: 4011_9ef4 XCCPART !TC1 || ADD #1,AC1
0x015c50: 121420 CMP AC1 < AC2, TC1
0x015c53: 046412 BCC #0x015c68,TC1
0x015c56: ed0428 MOV dbl(*SP(#02h)),AC2
0x015c59: 122c14 CMPU AC2 != AC1, TC1
0x015c5c: 04642e BCC #0x015c8d,TC1
0x015c5f: ed0818 MOV dbl(*SP(#04h)),AC1
0x015c62: 120814 CMPU AC0 >= AC1, TC1
0x015c65: 046425 BCC #0x015c8d,TC1
0x015c68: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015c6b: 7a80001a MOV #-32768 << #16,AC1
0x015c6f: 7b008000 ADD #128,AC0,AC0
0x015c73: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015c76: ed1408 MOV dbl(*SP(#0ah)),AC0
0x015c79: 120814 CMPU AC0 >= AC1, TC1
0x015c7c: 67e4 BCC #0x015c8d,TC1
0x015c7e: ed1808 MOV dbl(*SP(#0ch)),AC0
0x015c81: 4010 ADD #1,AC0
0x015c83: eb1808 MOV AC0,dbl(*SP(#0ch))
0x015c86: 7a80000a MOV #-32768 << #16,AC0
0x015c8a: eb1408 MOV AC0,dbl(*SP(#0ah))
0x015c8d: f4007fff AND #32767,*SP(#00h)
0x015c91: a100 MOV *SP(#00h),AC1
0x015c93: 7a80002a_2360 MOV #-32768 << #16,AC2 || MOV T2,AC0
0x015c99: 10410f OR AC0 << #15, AC1
0x015c9c: ec31be7fffff AMAR *(#07fffffh),XAR3
0x015ca2: c100 MOV AC1,*SP(#00h)
0x015ca4: ed0008 MOV dbl(*SP(#00h)),AC0
0x015ca7: 7a3f801a MOV #16256 << #16,AC1
0x015cab: ed1808_2902 MOV dbl(*SP(#0ch)),AC0 || AND AC0,AC2
0x015cb0: 100717 SFTL AC0,#23,AC0
0x015cb3: 2401 ADD AC0,AC1
0x015cb5: ec3e12 BCLR *SP(#1fh),AC1
0x015cb8: ed1408_2b21 MOV dbl(*SP(#0ah)),AC0 || OR AC2,AC1
0x015cbd: 108738 SFTL AC0,#-8,AC2
0x015cc0: 90b0 MOV XAR3,AC0
0x015cc2: 2820 AND AC2,AC0
0x015cc4: 2a10 OR AC1,AC0
0x015cc6: eb0008 MOV AC0,dbl(*SP(#00h))
0x015cc9: ed0008 MOV dbl(*SP(#00h)),AC0
0x015ccc: 4e0f AADD #15,SP
0x015cce: 3a76 POP T3,T2
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