Our customer needs clarification on the input clocks for c665x. We have previously advised them to review 6657 Data Manual and Keystone HW Guide (bottom on message here). They have returned with the following statements/questions....
I did not see any specifics in the data manual. However I did find the portion of the Keystone doc to which they are referring.
"All differential clock input buffers are low jitter clock buffers (LJCBs). These input
buffers include a 100 Ù parallel termination (P to N) and common mode biasing
(unless otherwise specified). Because the common mode biasing is included, the clock
source must be AC coupled (except where noted in this document and data sheet). Low
voltage differential swing (LVDS) and LVPECL clock sources are compatible with the
LJCBs."
One further question.
It seems as though many clocking solutions on the market output High Speed Current Steering Logic (HCSL).
If TI includes a 100ohm parallel term on the die for these inputs I am not sure if HCSL will be terminated properly. So to summarize the question.
" Are HCSL clock sources compatible with LJCB's?"
Also since the Keystone doc is being referenced that may raise some more questions. Can TI describe the relationship between these two docs
for so that I know in what level of detail, to review this keystone doc.
TI Repsonse to Original Question:
What voltage standard is required for the differential input clocks for the chip..primarily DDRCLK and CORECLK. ?
This information is contained in the C6657 Data Manual and the KeyStone Hardware Design Guide.
The reference clocks are LVDS tolerant. When AC-coupled, as recommended, any LVDS or LVPECL clock source can be used.
The C665x DSPs support the 2 separate power supply sequences to allow them to be implemented on boards that have other devices with specific power supply sequences. Both of these 2 sequences are equally valid and will be fully characterized. You should choose whichever sequence is best implemented on your board.
